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GET /api/patches/811554/?format=api
{ "id": 811554, "url": "http://patchwork.ozlabs.org/api/patches/811554/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-7-git-send-email-vjonnal@xilinx.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>", "list_archive_url": null, "date": "2017-09-08T12:23:08", "name": "[v2,5/5] devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "759a198a126e2e34d961e07b12220de84e80f0fe", "submitter": { "id": 72127, "url": "http://patchwork.ozlabs.org/api/people/72127/?format=api", "name": "Ravi Shankar Jonnalagadda", "email": "venkata.ravi.jonnalagadda@xilinx.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-7-git-send-email-vjonnal@xilinx.com/mbox/", "series": [ { "id": 2190, "url": "http://patchwork.ozlabs.org/api/series/2190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=2190", "date": "2017-09-08T12:23:04", "name": "dmaengine: ZynqMP PS PCIe DMA driver", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811554/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811554/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=xilinx.onmicrosoft.com\n\theader.i=@xilinx.onmicrosoft.com header.b=\"KlEse9S5\"; \n\tdkim-atps=neutral", "spf=pass (sender IP is 149.199.60.83)\n\tsmtp.mailfrom=xilinx.com; vger.kernel.org;\n\tdkim=none (message not signed)\n\theader.d=none;vger.kernel.org; dmarc=bestguesspass action=none\n\theader.from=xilinx.com;" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpc1m4JGFz9tXx\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 22:23:56 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755208AbdIHMXm (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 8 Sep 2017 08:23:42 -0400", "from mail-dm3nam03on0071.outbound.protection.outlook.com\n\t([104.47.41.71]:25184\n\t\"EHLO NAM03-DM3-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1754946AbdIHMXb (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tFri, 8 Sep 2017 08:23:31 -0400", "from BN6PR02CA0040.namprd02.prod.outlook.com (10.173.146.154) by\n\tCY1PR0201MB1930.namprd02.prod.outlook.com (10.163.56.28) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.35.12; 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\n\tclient-ip=149.199.60.83; helo=xsj-pvapsmtpgw01;", "From": "Ravi Shankar Jonnalagadda <venkata.ravi.jonnalagadda@xilinx.com>", "To": "<vinod.koul@intel.com>, <robh+dt@kernel.org>,\n\t<mark.rutland@arm.com>, <michal.simek@xilinx.com>,\n\t<soren.brinkmann@xilinx.com>, <dan.j.williams@intel.com>,\n\t<bhelgaas@google.com>, <vjonnal@xilinx.com>,\n\t<lorenzo.pieralisi@arm.com>, <bharat.kumar.gogada@xilinx.com>,\n\t<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<rgummal@xilinx.com>", "Subject": "[PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding for\n\tRoot DMA", "Date": "Fri, 8 Sep 2017 17:53:08 +0530", "Message-ID": "<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>", "X-Mailer": "git-send-email 2.1.1", "In-Reply-To": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "References": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "X-RCIS-Action": "ALLOW", "X-TM-AS-Product-Ver": "IMSS-7.1.0.1224-8.1.0.1062-23314.003", "X-TM-AS-User-Approved-Sender": "Yes;Yes", "X-EOPAttributedMessage": "0", "X-MS-Office365-Filtering-HT": "Tenant", "X-Forefront-Antispam-Report": "CIP:149.199.60.83; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR0201MB1930; ", "X-Forefront-PRVS": "04244E0DC5", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "xilinx.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2017 12:23:23.3567\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "657af505-d5df-48d0-8300-c31994686c5c", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=657af505-d5df-48d0-8300-c31994686c5c;\n\tIp=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0201MB1930", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Binding explaining devicetree usage for enabling Root DMA capability\n\nSigned-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com>\nSigned-off-by: RaviKiran Gummaluri <rgummal@xilinx.com>\n---\n .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++++++++++++++++++++++\n 1 file changed, 67 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt", "diff": "diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\nnew file mode 100644\nindex 0000000..1522a49\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n@@ -0,0 +1,67 @@\n+* Xilinx PS PCIe Root DMA\n+\n+Required properties:\n+- compatible: Should be \"xlnx,ps_pcie_dma-1.00.a\"\n+- reg: Register offset for Root DMA channels\n+- reg-names: Name for the register. Should be \"xlnx,ps_pcie_regbase\"\n+- interrupts: Interrupt pin for Root DMA\n+- interrupt-names: Name for the interrupt. Should be \"xlnx,ps_pcie_rootdma_intr\"\n+- interrupt-parent: Should be gic in case of zynqmp\n+- xlnx,rootdma: Indicates this platform device is root dma.\n+\tThis is required as the same platform driver will be invoked by pcie end points too\n+- xlnx,dma_vendorid: 16 bit PCIe device vendor id.\n+\tThis can be later used by dma client for matching while using dma_request_channel\n+- xlnx,dma_deviceid: 16 bit PCIe device id\n+\tThis can be later used by dma client for matching while using dma_request_channel\n+- xlnx,numchannels: Indicates number of channels to be enabled for the device.\n+\tValid values are from 1 to 4 for zynqmp\n+- xlnx,ps_pcie_channel : One for each channel to be enabled.\n+\tThis array contains channel specific properties.\n+\tIndex 0: Direction of channel\n+\t\tDirection of channel can be either PCIe Memory to AXI memory i.e., Host to Card or\n+\t\tAXI Memory to PCIe memory i.e., Card to Host\n+\t\tPCIe to AXI Channel Direction is represented as 0x1\n+\t\tAXI to PCIe Channel Direction is represented as 0x0\n+\tIndex 1: Number of Buffer Descriptors\n+\t\tThis number describes number of buffer descriptors to be allocated for a channel\n+\tIndex 2: Number of Queues\n+\t\tEach Channel has four DMA Buffer Descriptor Queues.\n+\t\tBy default All four Queues will be managed by Root DMA driver.\n+\t\tUser may choose to have only two queues either Source and it's Status Queue or\n+\t\t\tDestination and it's Status Queue to be handled by Driver.\n+\t\tThe other two queues need to be handled by user logic which will not be part of this driver.\n+\t\tAll Queues on Host is represented by 0x4\n+\t\tTwo Queues on Host is represented by 0x2\n+\tIndex 3: Coaelse Count\n+\t\tThis number indicates the number of transfers after which interrupt needs to\n+\t\tbe raised for the particular channel. The allowed range is from 0 to 255\n+\tIndex 4: Coaelse Count Timer frequency\n+\t\tThis property is used to control the frequency of poll timer. Poll timer is\n+\t\tcreated for a channel whenever coalesce count value (>= 1) is programmed for the particular\n+\t\tchannel. This timer is helpful in draining out completed transactions even though interrupt is\n+\t\tnot generated.\n+\n+Client Usage:\n+\tDMA clients can request for these channels using dma_request_channel API\n+\n+\n+Xilinx PS PCIe Root DMA node Example\n+++++++++++++++++++++++++++++++++++++\n+\n+\tpci_rootdma: rootdma@fd0f0000 {\n+\t\tcompatible = \"xlnx,ps_pcie_dma-1.00.a\";\n+\t\treg = <0x0 0xfd0f0000 0x0 0x1000>;\n+\t\treg-names = \"xlnx,ps_pcie_regbase\";\n+\t\tinterrupts = <0 117 4>;\n+\t\tinterrupt-names = \"xlnx,ps_pcie_rootdma_intr\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\txlnx,rootdma;\n+\t\txlnx,dma_vendorid = /bits/ 16 <0x10EE>;\n+\t\txlnx,dma_deviceid = /bits/ 16 <0xD021>;\n+\t\txlnx,numchannels = <0x4>;\n+\t\t#size-cells = <0x5>;\n+\t\txlnx,ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n+\t\txlnx,ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n+\t\txlnx,ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n+\t\txlnx,ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n+ };\n", "prefixes": [ "v2", "5/5" ] }