[{"id":1768141,"web_url":"http://patchwork.ozlabs.org/comment/1768141/","msgid":"<20170913202534.vf4r7dmuyfectbmv@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-13T20:25:34","subject":"Re: [PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding\n\tfor Root DMA","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Sep 08, 2017 at 05:53:08PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Binding explaining devicetree usage for enabling Root DMA capability\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++++++++++++++++++++++\n> 1 file changed, 67 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> \n> diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> new file mode 100644\n> index 0000000..1522a49\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> @@ -0,0 +1,67 @@\n> +* Xilinx PS PCIe Root DMA\n> +\n> +Required properties:\n> +- compatible: Should be \"xlnx,ps_pcie_dma-1.00.a\"\n> +- reg: Register offset for Root DMA channels\n> +- reg-names: Name for the register. Should be \"xlnx,ps_pcie_regbase\"\n\n*-names for a single entry is pointless.\n\n> +- interrupts: Interrupt pin for Root DMA\n> +- interrupt-names: Name for the interrupt. Should be \"xlnx,ps_pcie_rootdma_intr\"\n\nditto\n\n> +- interrupt-parent: Should be gic in case of zynqmp\n> +- xlnx,rootdma: Indicates this platform device is root dma.\n> +\tThis is required as the same platform driver will be invoked by pcie end points too\n\nplatform device and driver are Linux terms.\n\n> +- xlnx,dma_vendorid: 16 bit PCIe device vendor id.\n> +\tThis can be later used by dma client for matching while using dma_request_channel\n> +- xlnx,dma_deviceid: 16 bit PCIe device id\n> +\tThis can be later used by dma client for matching while using dma_request_channel\n\nThis is the id's of the client? Sounds like you should use the DMA \nbinding.\n\n> +- xlnx,numchannels: Indicates number of channels to be enabled for the device.\n> +\tValid values are from 1 to 4 for zynqmp\n\nDMA binding has a similar property.\n\n> +- xlnx,ps_pcie_channel : One for each channel to be enabled.\n\ns/_/-/\n\n> +\tThis array contains channel specific properties.\n> +\tIndex 0: Direction of channel\n> +\t\tDirection of channel can be either PCIe Memory to AXI memory i.e., Host to Card or\n> +\t\tAXI Memory to PCIe memory i.e., Card to Host\n> +\t\tPCIe to AXI Channel Direction is represented as 0x1\n> +\t\tAXI to PCIe Channel Direction is represented as 0x0\n> +\tIndex 1: Number of Buffer Descriptors\n> +\t\tThis number describes number of buffer descriptors to be allocated for a channel\n> +\tIndex 2: Number of Queues\n> +\t\tEach Channel has four DMA Buffer Descriptor Queues.\n> +\t\tBy default All four Queues will be managed by Root DMA driver.\n> +\t\tUser may choose to have only two queues either Source and it's Status Queue or\n> +\t\t\tDestination and it's Status Queue to be handled by Driver.\n> +\t\tThe other two queues need to be handled by user logic which will not be part of this driver.\n> +\t\tAll Queues on Host is represented by 0x4\n> +\t\tTwo Queues on Host is represented by 0x2\n> +\tIndex 3: Coaelse Count\n> +\t\tThis number indicates the number of transfers after which interrupt needs to\n> +\t\tbe raised for the particular channel. The allowed range is from 0 to 255\n> +\tIndex 4: Coaelse Count Timer frequency\n> +\t\tThis property is used to control the frequency of poll timer. Poll timer is\n> +\t\tcreated for a channel whenever coalesce count value (>= 1) is programmed for the particular\n> +\t\tchannel. This timer is helpful in draining out completed transactions even though interrupt is\n> +\t\tnot generated.\n> +\n> +Client Usage:\n> +\tDMA clients can request for these channels using dma_request_channel API\n> +\n> +\n> +Xilinx PS PCIe Root DMA node Example\n> +++++++++++++++++++++++++++++++++++++\n> +\n> +\tpci_rootdma: rootdma@fd0f0000 {\n\ndma-controller@...\n\n> +\t\tcompatible = \"xlnx,ps_pcie_dma-1.00.a\";\n> +\t\treg = <0x0 0xfd0f0000 0x0 0x1000>;\n> +\t\treg-names = \"xlnx,ps_pcie_regbase\";\n> +\t\tinterrupts = <0 117 4>;\n> +\t\tinterrupt-names = \"xlnx,ps_pcie_rootdma_intr\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\txlnx,rootdma;\n> +\t\txlnx,dma_vendorid = /bits/ 16 <0x10EE>;\n> +\t\txlnx,dma_deviceid = /bits/ 16 <0xD021>;\n> +\t\txlnx,numchannels = <0x4>;\n> +\t\t#size-cells = <0x5>;\n> +\t\txlnx,ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n> + };\n> -- \n> 2.7.4\n> \n> --\n> To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xstTH5C3bz9sDB\n\tfor ;\n\tThu, 14 Sep 2017 06:25:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752038AbdIMUZh (ORCPT );\n\tWed, 13 Sep 2017 16:25:37 -0400","from mail-io0-f196.google.com ([209.85.223.196]:35508 \"EHLO\n\tmail-io0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752022AbdIMUZg (ORCPT\n\t); Wed, 13 Sep 2017 16:25:36 -0400","by mail-io0-f196.google.com with SMTP id d16so1417052ioj.2;\n\tWed, 13 Sep 2017 13:25:36 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tw77sm6298176oie.8.2017.09.13.13.25.34\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 13 Sep 2017 13:25:34 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=HDLDerUyGOgKmavVeQS2Km81CRi+qkzyFw14Tj2pR88=;\n\tb=LEx0pp9f6qAw7q5UFgsVJGYG/R/KS9edo+Ja4Bex9S/5WQeMkrhy62yqx+Bnz8XybB\n\tCc6evGwxsKo5K5ivAvilef92U2MiHaWx4fHguE4VrVNnoWFmT3dpBJvRRwyo53dq5i/J\n\tckCDFT+50gS60/IMxxnw4WDim+d6eAAVM7xV8Wa+f85bgli2K+aVSrc1EDSBZ8AxigjW\n\t/0Vx302UePmrrgGGFjlmjdCDFi2yvx3cedfrjwXjityahXSS0ojOt+a+YCPqdpRTl/Nd\n\t/8Sx5HlK2UURUqo7ZYGXcccFucdn8F2BnGqbhXW0Z0DwfbwVqE3sNUKNNrBOBTx7tAPY\n\tlNNg==","X-Gm-Message-State":"AHPjjUh0b2kkjkqzEy0GSl9z77JqKbVUuY+coMw8A6IAvjTJVgX5NQ8F\n\t3r0aiR/2fQJ6ag==","X-Google-Smtp-Source":"AOwi7QCfTxXRgZrGMPpWY+bKobpy8zoxDv+2dXDGFHC2EiPI+j5+/Vn7i3jvUqCwLYfV02LJteqwCw==","X-Received":"by 10.202.184.215 with SMTP id\n\ti206mr20408621oif.285.1505334335467; \n\tWed, 13 Sep 2017 13:25:35 -0700 (PDT)","Date":"Wed, 13 Sep 2017 15:25:34 -0500","From":"Rob Herring ","To":"Ravi Shankar Jonnalagadda ","Cc":"vinod.koul@intel.com, mark.rutland@arm.com,\n\tmichal.simek@xilinx.com, soren.brinkmann@xilinx.com,\n\tdan.j.williams@intel.com, bhelgaas@google.com, vjonnal@xilinx.com,\n\tlorenzo.pieralisi@arm.com, bharat.kumar.gogada@xilinx.com,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, rgummal@xilinx.com","Subject":"Re: [PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding\n\tfor Root DMA","Message-ID":"<20170913202534.vf4r7dmuyfectbmv@rob-hp-laptop>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]