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GET /api/patches/810938/?format=api
{ "id": 810938, "url": "http://patchwork.ozlabs.org/api/patches/810938/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/00e7714871d7568e9fc848dc5f76d14e07984a1e.1504776489.git.talho@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<00e7714871d7568e9fc848dc5f76d14e07984a1e.1504776489.git.talho@nvidia.com>", "list_archive_url": null, "date": "2017-09-07T09:31:03", "name": "[3/4] reset: tegra: check BPMP response return code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "c4df96c58b077a89312ec9cbd4a3d20bc3123301", "submitter": { "id": 72177, "url": "http://patchwork.ozlabs.org/api/people/72177/?format=api", "name": "Timo Alho", "email": "talho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/00e7714871d7568e9fc848dc5f76d14e07984a1e.1504776489.git.talho@nvidia.com/mbox/", "series": [ { "id": 1959, "url": "http://patchwork.ozlabs.org/api/series/1959/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1959", "date": "2017-09-07T09:31:00", "name": "firmware: tegra: add checks for BPMP error return code", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1959/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810938/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810938/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnwJK6BWqz9t2M\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 19:34:09 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755204AbdIGJd7 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 7 Sep 2017 05:33:59 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:4786 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754894AbdIGJd5 (ORCPT\n\t<rfc822; linux-tegra@vger.kernel.org>); Thu, 7 Sep 2017 05:33:57 -0400", "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B59b1127f0000>; Thu, 07 Sep 2017 02:33:51 -0700", "from HQMAIL103.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tThu, 07 Sep 2017 02:33:46 -0700", "from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL103.nvidia.com\n\t(172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tThu, 7 Sep 2017 09:31:29 +0000", "from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL111.nvidia.com\n\t(172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tThu, 7 Sep 2017 09:31:28 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com\n\t(172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Thu, 7 Sep 2017 09:31:28 +0000", "from talho-ln2.nvidia.com (Not Verified[10.21.24.139]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid <B59b111ef0000>; Thu, 07 Sep 2017 02:31:28 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Thu, 07 Sep 2017 02:33:46 -0700", "From": "Timo Alho <talho@nvidia.com>", "To": "<thierry.reding@gmail.com>", "CC": "<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\tTimo Alho <talho@nvidia.com>", "Subject": "[PATCH 3/4] reset: tegra: check BPMP response return code", "Date": "Thu, 7 Sep 2017 12:31:03 +0300", "Message-ID": "<00e7714871d7568e9fc848dc5f76d14e07984a1e.1504776489.git.talho@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<cover.1504776489.git.talho@nvidia.com>", "References": "<cover.1504776489.git.talho@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "Add checks for return code in BPMP response message.\n\nSigned-off-by: Timo Alho <talho@nvidia.com>\n---\n drivers/reset/tegra/reset-bpmp.c | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/reset/tegra/reset-bpmp.c b/drivers/reset/tegra/reset-bpmp.c\nindex 5daf2ee..fac2db6 100644\n--- a/drivers/reset/tegra/reset-bpmp.c\n+++ b/drivers/reset/tegra/reset-bpmp.c\n@@ -23,6 +23,7 @@ static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,\n \tstruct tegra_bpmp *bpmp = to_tegra_bpmp(rstc);\n \tstruct mrq_reset_request request;\n \tstruct tegra_bpmp_message msg;\n+\tint err;\n \n \tmemset(&request, 0, sizeof(request));\n \trequest.cmd = command;\n@@ -33,7 +34,13 @@ static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,\n \tmsg.tx.data = &request;\n \tmsg.tx.size = sizeof(request);\n \n-\treturn tegra_bpmp_transfer(bpmp, &msg);\n+\terr = tegra_bpmp_transfer(bpmp, &msg);\n+\tif (err < 0)\n+\t\treturn err;\n+\telse if (msg.rx.ret < 0)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n }\n \n static int tegra_bpmp_reset_module(struct reset_controller_dev *rstc,\n", "prefixes": [ "3/4" ] }