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GET /api/patches/810731/?format=api
{ "id": 810731, "url": "http://patchwork.ozlabs.org/api/patches/810731/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504717175-11844-1-git-send-email-suneelglinux@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504717175-11844-1-git-send-email-suneelglinux@gmail.com>", "list_archive_url": null, "date": "2017-09-06T16:59:35", "name": "[U-Boot,v1] drivers: ahci: write upper 32 bits for clb and fis registers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "e06692d138646b7062718a45dd4c8abf6c316ea8", "submitter": { "id": 72058, "url": "http://patchwork.ozlabs.org/api/people/72058/?format=api", "name": "Suneel Garapati", "email": "suneelglinux@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504717175-11844-1-git-send-email-suneelglinux@gmail.com/mbox/", "series": [ { "id": 1856, "url": "http://patchwork.ozlabs.org/api/series/1856/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1856", "date": "2017-09-06T16:59:35", "name": "[U-Boot,v1] drivers: ahci: write upper 32 bits for clb and fis registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1856/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810731/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"gHDpPWFE\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnVF02Lymz9t2d\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:59:48 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 08932C21EFD; Wed, 6 Sep 2017 16:59:45 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CC15DC21E3B;\n\tWed, 6 Sep 2017 16:59:43 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 5F8FAC21E3B; Wed, 6 Sep 2017 16:59:43 +0000 (UTC)", "from mail-pf0-f195.google.com (mail-pf0-f195.google.com\n\t[209.85.192.195])\n\tby lists.denx.de (Postfix) with ESMTPS id C8CE1C21E11\n\tfor <u-boot@lists.denx.de>; Wed, 6 Sep 2017 16:59:42 +0000 (UTC)", "by mail-pf0-f195.google.com with SMTP id m1so3313503pfk.0\n\tfor <u-boot@lists.denx.de>; Wed, 06 Sep 2017 09:59:42 -0700 (PDT)", "from suneel.hsd1.ca.comcast.net\n\t([2601:646:8e00:e521:a8ab:948d:75cf:79c4])\n\tby smtp.gmail.com with ESMTPSA id\n\tj10sm365556pfj.116.2017.09.06.09.59.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 06 Sep 2017 09:59:40 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=PifiLok7libgwTrLIjATtIM5d4JpKuq/4U0m9t2C8DQ=;\n\tb=gHDpPWFEMNgvcnt4U6JZ1ZMAfxXcX9wOAL5+gVwDDLFqVbe7IEGBI7njcJuA/eQx2U\n\t8Klso+N99wVGHlJTyf2eCaSZgtxBR/eBpvZhCjMp7hV4CzhVAZRF7tPdhcWee/K2T5vD\n\tnsvLaA4ikWqlDvcmgnZwX1Coy+OwAeBT9ShSfEyU+SiKn89fTuZd0RS1cgeyJuzlqdnv\n\trbus1Kf3UQEJ2XK12I99oT1xc+huEX1Sz1P3xCCd9UeRyP2HbonQYNlIsErodTQ9rMEP\n\t+SMeENiFRRGQXOFZOSdpVUBK3c5q9PPsVK4eucBZH9oqNuohGh4PL1SSZTVKAU+Y64Sm\n\tF80g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=PifiLok7libgwTrLIjATtIM5d4JpKuq/4U0m9t2C8DQ=;\n\tb=dwg/QZyLIOGg5tYV2b63qB6ggx1suVGxofh+mCj4ux6LuRNEvqlVbNliQ5qIl+zccZ\n\t5RPqWOdQNKkYhPlxwyKBu6CpIRMVnmUg6jVr4LXvUxaiYeAP6232X7L2MEfnYfIz9sMS\n\tpfDAxx2s97OAcUvdw0FCx4T5xGWerJ7fklUtw6/Wpms+OAABRo2z+DD9h3KuM/+Q8xdC\n\trSQ0MDVEuaXCZkC9GZgwEaQhmTD8H5bhzUWu0oi/9NWOIWwL2GO2z0Es6JrUsK3v2CdB\n\tbtzEGXzOcLifx+NzeSCol8tVeaevdp0AWNTIwVdIHrdUnKAWi6Mwo4wc3xc4eDu86/tF\n\tVKLg==", "X-Gm-Message-State": "AHPjjUgF5b+cgj7nRI8zIVsKb82qwcupaDDCazZhCzGs0mw6ePJTYuMF\n\towZkKawzz9sHIj2Y", "X-Google-Smtp-Source": "ADKCNb5DSEKQSEXv10TuPZAQd/RvuiRJUPvHwMBOjCqP30C9rnY9HE4G+u9iDAj7TbphxFHcUpS/Zg==", "X-Received": "by 10.98.33.134 with SMTP id o6mr7931207pfj.103.1504717181155;\n\tWed, 06 Sep 2017 09:59:41 -0700 (PDT)", "From": "Suneel Garapati <suneelglinux@gmail.com>", "To": "Bin Meng <bmeng.cn@gmail.com>", "Date": "Wed, 6 Sep 2017 09:59:35 -0700", "Message-Id": "<1504717175-11844-1-git-send-email-suneelglinux@gmail.com>", "X-Mailer": "git-send-email 2.7.4", "Cc": "u-boot@lists.denx.de, Michal Simek <michal.simek@xilinx.com>", "Subject": "[U-Boot] [PATCH v1] drivers: ahci: write upper 32 bits for clb and\n\tfis registers", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "If 64-bit capability is supported, commandlistbase and fis base\nshould be split as lower32 and upper32. upper32 should be\nwritten to PORT_(LST/FIS)_ADDR_HI.\n\nSigned-off-by: Suneel Garapati <suneelglinux@gmail.com>\n---\n\nChanges v1:\n - add macro definitions for LOWER32, UPPER32\n\n\n drivers/ata/ahci.c | 14 ++++++++++++--\n include/ahci.h | 1 +\n 2 files changed, 13 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c\nindex 5e4df19..178d9a7 100644\n--- a/drivers/ata/ahci.c\n+++ b/drivers/ata/ahci.c\n@@ -27,6 +27,9 @@\n #include <dm/device-internal.h>\n #include <dm/lists.h>\n \n+#define LOWER32(val)\t(u32)((u64)(val) & 0xFFFFFFFF)\n+#define UPPER32(val)\t(u32)(((u64)(val) & 0xFFFFFFFF00000000ULL) >> 32)\n+\n static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);\n \n #ifndef CONFIG_DM_SCSI\n@@ -607,10 +610,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)\n \tpp->cmd_tbl_sg =\n \t\t\t(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);\n \n-\twritel_with_flush((unsigned long)pp->cmd_slot,\n+\tif (uc_priv->cap & HOST_CAP_64)\n+\t\twritel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)),\n+\t\t\t\t port_mmio + PORT_LST_ADDR_HI);\n+\twritel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)),\n \t\t\t port_mmio + PORT_LST_ADDR);\n \n-\twritel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);\n+\tif (uc_priv->cap & HOST_CAP_64)\n+\t\twritel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)),\n+\t\t\t\t port_mmio + PORT_FIS_ADDR_HI);\n+\twritel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)),\n+\t\t\t port_mmio + PORT_FIS_ADDR);\n \n #ifdef CONFIG_SUNXI_AHCI\n \tsunxi_dma_init(port_mmio);\ndiff --git a/include/ahci.h b/include/ahci.h\nindex 33171b7..80e7f13 100644\n--- a/include/ahci.h\n+++ b/include/ahci.h\n@@ -40,6 +40,7 @@\n #define HOST_RESET\t\t(1 << 0) /* reset controller; self-clear */\n #define HOST_IRQ_EN\t\t(1 << 1) /* global IRQ enable */\n #define HOST_AHCI_EN\t\t(1 << 31) /* AHCI enabled */\n+#define HOST_CAP_64\t\t(1 << 31) /* 64bit addressing capability */\n \n /* Registers for each SATA port */\n #define PORT_LST_ADDR\t\t0x00 /* command list DMA addr */\n", "prefixes": [ "U-Boot", "v1" ] }