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{ "id": 810673, "url": "http://patchwork.ozlabs.org/api/patches/810673/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/1504711323.18797.5.camel@us.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504711323.18797.5.camel@us.ibm.com>", "list_archive_url": null, "date": "2017-09-06T15:22:03", "name": "[rs6000] Add support for vec_xst_len_r() and vec_xl_len_r() builtins", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "56d04a7567c4136b5d0c7dbd3db22b1c437e828f", "submitter": { "id": 1003, "url": "http://patchwork.ozlabs.org/api/people/1003/?format=api", "name": "Carl Love", "email": "cel@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/1504711323.18797.5.camel@us.ibm.com/mbox/", "series": [ { "id": 1835, "url": "http://patchwork.ozlabs.org/api/series/1835/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1835", "date": "2017-09-06T15:22:03", "name": "[rs6000] Add support for vec_xst_len_r() and vec_xl_len_r() builtins", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1835/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810673/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810673/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461621-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461621-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"Yl3qksA8\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnS4j1C3dz9t2R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 01:22:27 +1000 (AEST)", "(qmail 48172 invoked by alias); 6 Sep 2017 15:22:17 -0000", "(qmail 48147 invoked by uid 89); 6 Sep 2017 15:22:17 -0000", "from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.158.5) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 06 Sep 2017 15:22:09 +0000", "from pps.filterd (m0098416.ppops.net [127.0.0.1])\tby\n\tmx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv86FL0bB176075\tfor <gcc-patches@gcc.gnu.org>;\n\tWed, 6 Sep 2017 11:22:08 -0400", "from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152])\tby\n\tmx0b-001b2d01.pphosted.com with ESMTP id\n\t2ctfxvphmr-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor <gcc-patches@gcc.gnu.org>;\n\tWed, 06 Sep 2017 11:22:07 -0400", "from localhost\tby e34.co.us.ibm.com with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! 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The patch has been run on\npowerpc64le-unknown-linux-gnu (Power 9 LE). No regressions were found\nbut it does seem to \"fix\" a couple of existing tests.\n\n136a137\n> FAIL: TestCgoCallbackGC\n139c140,141\n< # of expected passes\t\t350\n---\n> # of expected passes\t\t349\n> # of unexpected failures\t1\n141c143\n< /home/carll/GCC/build/gcc-builtin-pre-commit/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC)\n---\n> /home/carll/GCC/build/gcc-base/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC)\n163a166\n> FAIL: html/template\n167,168c170,172\n< # of expected passes\t\t146\n< /home/carll/GCC/build/gcc-builtin-pre-commit/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC)\n---\n> # of expected passes\t\t145\n> # of unexpected failures\t1\n> /home/carll/GCC/build/gcc-base/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC)\n \n\nPlease let me know if the following patch is acceptable. Thanks.\n\n Carl Love\n\n------------------------------------------------------------------------\n\ngcc/ChangeLog:\n\n2017-09-06 Carl Love <cel@us.ibm.com>\n\n\t* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R,\n\tP9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins\n\tvector unsigned char vec_xl_len_r (unsigned char *, size_t);\n\tvoid vec_xst_len_r (vector unsigned char, unsigned char *, size_t);\n\t* config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines.\n\t* config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add\n\tdefinitions and overloading.\n\t* config/rs6000/rs6000.c (altivec_expand_builtin): Add case\n\tstatement for P9V_BUILTIN_XST_LEN_R.\n\t(altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL.\n\t* config/rs6000/vsx.md (addi_neg16, lxvll, stxvll, altivec_lvsl_reg,\n\taltivec_lvsr_reg, xl_len_r, xst_len_r): Add define_expand and\n\tdefine_insn for the instructions and builtins.\n\t(define_insn \"*stxvl\"): add missing argument to the sldi instruction.\n\t* doc/extend.texi: Update the built-in documenation file for the new\n\tbuilt-in functions.\n\ngcc/testsuite/ChangeLog:\n\n2017-09-06 Carl Love <cel@us.ibm.com>\n\n\t* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file\n\tfor the new built-ins and the existing built-ins.\n---\n gcc/config/rs6000/altivec.h | 2 +\n gcc/config/rs6000/rs6000-builtin.def | 4 +\n gcc/config/rs6000/rs6000-c.c | 8 +\n gcc/config/rs6000/rs6000.c | 7 +-\n gcc/config/rs6000/vsx.md | 133 ++++++++-\n gcc/doc/extend.texi | 4 +\n .../gcc.target/powerpc/builtins-5-p9-runnable.c | 309 +++++++++++++++++++++\n 7 files changed, 465 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c", "diff": "diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h\nindex c8e508c..94a4db2 100644\n--- a/gcc/config/rs6000/altivec.h\n+++ b/gcc/config/rs6000/altivec.h\n@@ -467,6 +467,8 @@\n #ifdef _ARCH_PPC64\n #define vec_xl_len __builtin_vec_lxvl\n #define vec_xst_len __builtin_vec_stxvl\n+#define vec_xl_len_r __builtin_vec_xl_len_r\n+#define vec_xst_len_r __builtin_vec_xst_len_r\n #endif\n \n #define vec_cmpnez __builtin_vec_vcmpnez\ndiff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def\nindex 850164a..8f87cce 100644\n--- a/gcc/config/rs6000/rs6000-builtin.def\n+++ b/gcc/config/rs6000/rs6000-builtin.def\n@@ -2125,6 +2125,7 @@ BU_P9V_OVERLOAD_2 (VIESP,\t\"insert_exp_sp\")\n \n /* 2 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_64BIT_VSX_2 (LXVL,\t\"lxvl\",\t\tCONST,\tlxvl)\n+BU_P9V_64BIT_VSX_2 (XL_LEN_R,\t\"xl_len_r\",\tCONST, xl_len_r)\n \n BU_P9V_AV_2 (VEXTUBLX, \"vextublx\",\t\tCONST,\tvextublx)\n BU_P9V_AV_2 (VEXTUBRX, \"vextubrx\",\t\tCONST,\tvextubrx)\n@@ -2141,6 +2142,7 @@ BU_P9V_VSX_3 (VINSERT4B_DI, \"vinsert4b_di\",\tCONST,\tvinsert4b_di)\n /* 3 argument vector functions returning void, treated as SPECIAL,\n added in ISA 3.0 (power9). */\n BU_P9V_64BIT_AV_X (STXVL,\t\"stxvl\",\tMISC)\n+BU_P9V_64BIT_AV_X (XST_LEN_R,\t\"xst_len_r\",\tMISC)\n \n /* 1 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_AV_1 (VCLZLSBB, \"vclzlsbb\",\t\tCONST,\tvclzlsbb)\n@@ -2182,12 +2184,14 @@ BU_P9V_AV_P (VCMPNEZW_P,\t\"vcmpnezw_p\",\tCONST,\tvector_nez_v4si_p)\n \n /* ISA 3.0 Vector scalar overloaded 2 argument functions */\n BU_P9V_OVERLOAD_2 (LXVL,\t\"lxvl\")\n+BU_P9V_OVERLOAD_2 (XL_LEN_R,\t\"xl_len_r\")\n BU_P9V_OVERLOAD_2 (VEXTULX,\t\"vextulx\")\n BU_P9V_OVERLOAD_2 (VEXTURX,\t\"vexturx\")\n BU_P9V_OVERLOAD_2 (VEXTRACT4B,\t\"vextract4b\")\n \n /* ISA 3.0 Vector scalar overloaded 3 argument functions */\n BU_P9V_OVERLOAD_3 (STXVL,\t\"stxvl\")\n+BU_P9V_OVERLOAD_3 (XST_LEN_R,\t\"xst_len_r\")\n BU_P9V_OVERLOAD_3 (VINSERT4B,\t\"vinsert4b\")\n \n /* Overloaded CMPNE support was implemented prior to Power 9,\ndiff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c\nindex 897306c..15f0406 100644\n--- a/gcc/config/rs6000/rs6000-c.c\n+++ b/gcc/config/rs6000/rs6000-c.c\n@@ -4787,6 +4787,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,\n RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },\n \n+ { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,\n+ RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,\n+ RS6000_BTI_unsigned_long_long, 0 },\n+\n { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,\n RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long, 0 },\n@@ -4831,6 +4835,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n /* At an appropriate future time, add support for the\n RS6000_BTI_Float16 (exact name to be determined) type here. */\n \n+ { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,\n+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,\n+ ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},\n+\n { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,\n RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long },\ndiff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c\nindex 6d613c3..6df2d79 100644\n--- a/gcc/config/rs6000/rs6000.c\n+++ b/gcc/config/rs6000/rs6000.c\n@@ -15580,6 +15580,8 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)\n case P9V_BUILTIN_STXVL:\n return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);\n \n+ case P9V_BUILTIN_XST_LEN_R:\n+ return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);\n case VSX_BUILTIN_STXVD2X_V1TI:\n return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);\n case VSX_BUILTIN_STXVD2X_V2DF:\n@@ -17534,9 +17536,12 @@ altivec_init_builtins (void)\n def_builtin (\"__builtin_vec_stvrx\", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);\n def_builtin (\"__builtin_vec_stvrxl\", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);\n \n- if (TARGET_P9_VECTOR)\n+ if (TARGET_P9_VECTOR) {\n def_builtin (\"__builtin_altivec_stxvl\", void_ftype_v16qi_pvoid_long,\n \t\t P9V_BUILTIN_STXVL);\n+ def_builtin (\"__builtin_xst_len_r\", void_ftype_v16qi_pvoid_long,\n+\t\t P9V_BUILTIN_XST_LEN_R);\n+ }\n \n /* Add the DST variants. */\n d = bdesc_dst;\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex b47eeac..b9c7343 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -382,8 +382,17 @@\n UNSPEC_VSX_VTSTDC\n UNSPEC_VSX_VEC_INIT\n UNSPEC_VSX_VSIGNED2\n+\n+ UNSPEC_ADDI_NEG16\n UNSPEC_LXVL\n+ UNSPEC_LXVLL\n+ UNSPEC_LVSL_REG\n+ UNSPEC_LVSR_REG\n UNSPEC_STXVL\n+ UNSPEC_STXVLL\n+ UNSPEC_XL_LEN_R\n+ UNSPEC_XST_LEN_R\n+\n UNSPEC_VCLZLSBB\n UNSPEC_VCTZLSBB\n UNSPEC_VEXTUBLX\n@@ -4352,6 +4361,106 @@\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecload\")])\n \n+(define_insn \"addi_neg16\"\n+ [(set (match_operand:DI 0 \"vsx_register_operand\" \"=r\")\n+ (unspec:DI\n+ [(match_operand:DI 1 \"gpc_reg_operand\" \"r\")]\n+ UNSPEC_ADDI_NEG16))]\n+ \"\"\n+ \"addi %0,%1,-16\"\n+)\n+\n+;; Load VSX Vector with Length, right justified\n+(define_expand \"lxvll\"\n+ [(set (match_dup 3)\n+ (match_operand:DI 2 \"register_operand\"))\n+ (set (match_operand:V16QI 0 \"vsx_register_operand\")\n+\t(unspec:V16QI\n+\t [(match_operand:DI 1 \"gpc_reg_operand\")\n+\t (match_dup 3)]\n+\t UNSPEC_LXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+{\n+ operands[3] = gen_reg_rtx (DImode);\n+})\n+\n+(define_insn \"*lxvll\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V16QI\n+\t [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n+\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n+\t UNSPEC_LXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+;; \"lxvll %x0,%1,%2;\"\n+ \"sldi %2,%2, 56\\; lxvll %x0,%1,%2;\"\n+ [(set_attr \"length\" \"8\")\n+ (set_attr \"type\" \"vecload\")])\n+\n+(define_insn \"altivec_lvsl_reg\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (unspec:V16QI\n+ [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+ UNSPEC_LVSL_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsl %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n+(define_insn \"altivec_lvsr_reg\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (unspec:V16QI\n+ [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+ UNSPEC_LVSR_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsr %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n+;; Expand for builtin xl_len_r\n+(define_expand \"xl_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (match_operand:DI 1 \"register_operand\" \"r\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"UNSPEC_XL_LEN_R\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+/* Setup permute vector to shift right by operands[2] bytes.\n+ Note: addi operands[2], -16 is negative so we actually need to\n+ shift left to get a right shift. */\n+ emit_insn (gen_addi_neg16 (tmp, operands[2]));\n+ emit_insn (gen_altivec_lvsl_reg (shift_mask, tmp));\n+ emit_insn (gen_lxvll (rtx_vtmp, operands[1], operands[2]));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp,\n+\t\t\t\t\t rtx_vtmp, shift_mask));\n+ DONE;\n+})\n+\n+;; Store VSX Vector with Length, right justified\n+(define_expand \"stxvll\"\n+ [(set (match_dup 3)\n+\t(match_operand:DI 2 \"register_operand\"))\n+ (set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\"))\n+\t(unspec:V16QI\n+\t [(match_operand:V16QI 0 \"vsx_register_operand\")\n+\t (match_dup 3)]\n+\t UNSPEC_STXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+{\n+ operands[3] = gen_reg_rtx (DImode);\n+})\n+\n+(define_insn \"*stxvll\"\n+ [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n+\t(unspec:V16QI\n+\t [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n+\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n+\t UNSPEC_STXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+ \"sldi %2,%2,56\\;stxvll %x0,%1,%2\"\n+ [(set_attr \"length\" \"8\")\n+ (set_attr \"type\" \"vecstore\")])\n+\n ;; Store VSX Vector with Length\n (define_expand \"stxvl\"\n [(set (match_dup 3)\n@@ -4373,10 +4482,32 @@\n \t (match_operand:DI 2 \"register_operand\" \"+r\")]\n \t UNSPEC_STXVL))]\n \"TARGET_P9_VECTOR && TARGET_64BIT\"\n- \"sldi %2,%2\\;stxvl %x0,%1,%2\"\n+ \"sldi %2,%2,56\\;stxvl %x0,%1,%2\"\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecstore\")])\n \n+;; Expand for builtin xst_len_r\n+(define_expand \"xst_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (match_operand:DI 1 \"register_operand\" \"r\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"UNSPEC_XST_LEN_R\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+/* Setup permute vector to shift left by operands[2] bytes.\n+ Note: addi operands[2], -16 is negative so we actually need to\n+ shift right to get a left shift. */\n+ emit_insn (gen_addi_neg16 (tmp, operands[2]));\n+ emit_insn (gen_altivec_lvsr_reg (shift_mask, tmp));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0],\n+\t\t\t\t\t operands[0], shift_mask));\n+ emit_insn (gen_stxvll (rtx_vtmp, operands[1], operands[2]));\n+ DONE;\n+})\n+\n ;; Vector Compare Not Equal Byte\n (define_insn \"vcmpneb\"\n [(set (match_operand:V16QI 0 \"altivec_register_operand\" \"=v\")\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 649be01..37fd769 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -15631,6 +15631,8 @@ vector unsigned short vec_xl_len (unsigned short *addr, size_t len);\n vector double vec_xl_len (double *addr, size_t len);\n vector float vec_xl_len (float *addr, size_t len);\n \n+vector unsigned char vec_xl_len_r (unsigned char *addr, size_t len);\n+\n void vec_xst_len (vector signed char data, signed char *addr, size_t len);\n void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);\n void vec_xst_len (vector signed int data, signed int *addr, size_t len);\n@@ -15644,6 +15646,8 @@ void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len\n void vec_xst_len (vector double data, double *addr, size_t len);\n void vec_xst_len (vector float data, float *addr, size_t len);\n \n+void vec_xst_len_r (vector unsigned char data, unsigned char *addr, size_t len);\n+\n signed char vec_xlx (unsigned int index, vector signed char data);\n unsigned char vec_xlx (unsigned int index, vector unsigned char data);\n signed short vec_xlx (unsigned int index, vector signed short data);\ndiff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\nnew file mode 100644\nindex 0000000..448e974\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n@@ -0,0 +1,309 @@\n+/* { dg-do run { target { powerpc64*-*-* && { p9vector_hw } } } } */\n+/* { dg-skip-if \"do not override -mcpu\" { powerpc*-*-* } { \"-mcpu=*\" } { \"-mcpu=power9\" } } */\n+/* { dg-options \"-mcpu=power9 -O2\" } */\n+\n+#include <stdint.h>\n+#include <stdio.h> \n+#include <inttypes.h>\n+#include <altivec.h> // vector\n+\n+#define TRUE 1\n+#define FALSE 0\n+\n+#ifdef DEBUG\n+#include <stdio.h>\n+#endif\n+\n+void abort (void);\n+\n+int result_wrong(vector unsigned char vec_expected,\n+\t\t vector unsigned char vec_actual)\n+{\n+ int i;\n+\n+ for (i=0; i<16; i++)\n+ if (vec_expected[i] != vec_actual[i])\n+ return TRUE;\n+\n+ return FALSE;\n+}\n+\n+int main() {\n+ int i, j;\n+ size_t size;\n+ unsigned char data_uc[100];\n+ vector unsigned char store_data_uc;\n+ unsigned char *address;\n+ vector unsigned char *datap;\n+ \n+ vector unsigned char vec_uc_expected1, vec_uc_expected2,\n+ vec_uc_result1, vec_uc_result2;\n+ vector int data_int;\n+ \n+ for (i=0; i<100; i++)\n+ data_uc[i] = i+1;\n+\n+ \n+ /* VEC_XL_LEN */\n+ \n+ size = 8;\n+ vec_uc_result1 = vec_xl_len (data_uc, size);\n+\n+ vec_uc_expected1 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 0, 0, 0, 0, 0, 0, 0, 0};\n+ \n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len (%d): vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\",vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xl_len (%d): vec_uc_result1[0] to vec_uc_result1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XL_LEN_R */\n+ size = 8;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){8, 7, 6, 5, 4, 3, 2, 1,\n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0,};\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+ \n+\n+ size = 4;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 4, 3, 2, 1, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ size = 2;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XST_LEN */\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+ \n+ address = &vec_uc_result2[0];\n+ vec_xst_len (store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+\n+ address = &vec_uc_result2[0];\n+\n+ vec_xst_len (store_data_uc, address, size);\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ /* VEC_XST_LEN_R */\n+ vec_uc_expected1 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ vec_uc_expected1 = (vector unsigned char){ 14, 13, 12, 11, 10, 9, 8, 7,\n+ 6, 5, 4, 3, 2, 1, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+}\n", "prefixes": [ "rs6000" ] }