[{"id":1764318,"web_url":"http://patchwork.ozlabs.org/comment/1764318/","msgid":"<20170906191426.GL13471@gate.crashing.org>","list_archive_url":null,"date":"2017-09-06T19:14:26","subject":"Re: [PATCH,\n\trs6000] Add support for vec_xst_len_r() and vec_xl_len_r() builtins","submitter":{"id":134,"url":"http://patchwork.ozlabs.org/api/people/134/","name":"Segher Boessenkool","email":"segher@kernel.crashing.org"},"content":"Hi Carl,\n\nOn Wed, Sep 06, 2017 at 08:22:03AM -0700, Carl Love wrote:\n> \t(define_insn \"*stxvl\"): add missing argument to the sldi instruction.\n\ns/add/Add/ . This one-liner fix is approved right now, please commit\nit as a separate patch.\n\n\n> +(define_insn \"addi_neg16\"\n> + [(set (match_operand:DI 0 \"vsx_register_operand\" \"=r\")\n> + (unspec:DI\n> + [(match_operand:DI 1 \"gpc_reg_operand\" \"r\")]\n> + UNSPEC_ADDI_NEG16))]\n> + \"\"\n> + \"addi %0,%1,-16\"\n> +)\n\nYou don't need a separate insn (or unspec) for this at all afaics...\nWhere you do\n\n emit_insn (gen_addi_neg16 (tmp, operands[2]));\n\nyou could just do\n\n emit_insn (gen_adddi3 (tmp, operands[2], GEN_INT (-16)));\n\n\n> +;; Load VSX Vector with Length, right justified\n> +(define_expand \"lxvll\"\n> + [(set (match_dup 3)\n> + (match_operand:DI 2 \"register_operand\"))\n> + (set (match_operand:V16QI 0 \"vsx_register_operand\")\n> +\t(unspec:V16QI\n> +\t [(match_operand:DI 1 \"gpc_reg_operand\")\n> +\t (match_dup 3)]\n> +\t UNSPEC_LXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> +{\n> + operands[3] = gen_reg_rtx (DImode);\n> +})\n\nHrm, so you make a reg 3 only because the lxvll pattern will clobber it?\n\n> +(define_insn \"*lxvll\"\n> + [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V16QI\n> +\t [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n> +\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n> +\t UNSPEC_LXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> +;; \"lxvll %x0,%1,%2;\"\n> + \"sldi %2,%2, 56\\; lxvll %x0,%1,%2;\"\n> + [(set_attr \"length\" \"8\")\n> + (set_attr \"type\" \"vecload\")])\n\nIt is nicer to just have a match_scratch in here then, like\n\n(define_insn \"*lxvll\"\n [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n\t(unspec:V16QI\n\t [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n\t (match_operand:DI 2 \"register_operand\" \"r\")]\n\t UNSPEC_LXVLL))\n (clobber (match_scratch:DI 3 \"=&r\"))]\n \"TARGET_P9_VECTOR && TARGET_64BIT\"\n \"sldi %3,%2,56\\;lxvll %x0,%1,%3\"\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecload\")])\n\n(Note spacing, comment, \";\" stuff, and the earlyclobber).\n\nIdeally you split the sldi off in the expand though, so that the *lxvll\npattern is really just that single insn.\n\n\n> +(define_insn \"altivec_lvsl_reg\"\n> + [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n> + (unspec:V16QI\n> + [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n> + UNSPEC_LVSL_REG))]\n> + \"TARGET_ALTIVEC\"\n> + \"lvsl %0,0,%1\"\n> + [(set_attr \"type\" \"vecload\")])\n\nvecload isn't really the correct type for this, but I see we have the\nsame on the existing lvsl patterns (it's permute unit on p9; I expect\nthe same on p8 and older, but please check).\n\nPlease move this next to the existing lvsl pattern.\n\n\n> +;; Expand for builtin xl_len_r\n> +(define_expand \"xl_len_r\"\n> + [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n> + (match_operand:DI 1 \"register_operand\" \"r\")\n> + (match_operand:DI 2 \"register_operand\" \"r\")]\n> + \"UNSPEC_XL_LEN_R\"\n> +{\n> + rtx shift_mask = gen_reg_rtx (V16QImode);\n> + rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n> + rtx tmp = gen_reg_rtx (DImode);\n> +\n> +/* Setup permute vector to shift right by operands[2] bytes.\n> + Note: addi operands[2], -16 is negative so we actually need to\n> + shift left to get a right shift. */\n\nIndent the comment with the code, so that's 2 spaces more here.\n\nThe comment isn't clear to me... Neither is the code though: lvsl\nlooks at just the low 4 bits of its arg, so the addi does nothing\nuseful? Maybe I am missing something.\n\n> + emit_insn (gen_addi_neg16 (tmp, operands[2]));\n> + emit_insn (gen_altivec_lvsl_reg (shift_mask, tmp));\n> + emit_insn (gen_lxvll (rtx_vtmp, operands[1], operands[2]));\n> + emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp,\n> +\t\t\t\t\t rtx_vtmp, shift_mask));\n\n\n\n> +;; Store VSX Vector with Length, right justified\n\n_left_ justified?\n\n> +(define_expand \"stxvll\"\n> + [(set (match_dup 3)\n> +\t(match_operand:DI 2 \"register_operand\"))\n> + (set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\"))\n> +\t(unspec:V16QI\n> +\t [(match_operand:V16QI 0 \"vsx_register_operand\")\n> +\t (match_dup 3)]\n> +\t UNSPEC_STXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> +{\n> + operands[3] = gen_reg_rtx (DImode);\n> +})\n\n\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n> @@ -0,0 +1,309 @@\n> +/* { dg-do run { target { powerpc64*-*-* && { p9vector_hw } } } } */\n\nThis should be powerpc*-*-* I think? Does it need braces around\np9vector_hw?\n\n\nSegher","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461641-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"OOfGYVCY\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnYH04lNfz9t34\n\tfor ;\n\tThu, 7 Sep 2017 05:16:42 +1000 (AEST)","(qmail 51045 invoked by alias); 6 Sep 2017 19:14:34 -0000","(qmail 50387 invoked by uid 89); 6 Sep 2017 19:14:33 -0000","from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by\n\tsourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 06 Sep 2017 19:14:32 +0000","from gate.crashing.org (localhost.localdomain [127.0.0.1])\tby\n\tgate.crashing.org (8.14.1/8.13.8) with ESMTP id\n\tv86JERDj014622; Wed, 6 Sep 2017 14:14:28 -0500","(from segher@localhost)\tby gate.crashing.org\n\t(8.14.1/8.14.1/Submit) id v86JERwS014621;\n\tWed, 6 Sep 2017 14:14:27 -0500"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; q=dns; s=default; b=Ghji6hR+iLiMtGneU\n\tbWZaHb3OEwIj2EfiZWra6DGxQ7ycwFykuHlSBUWP/3usT0OIIfNb11QniykT9rn3\n\toGoZsb5RPdkB3nWBqCNZs8L/yLuK6q3UFlnYy098HVKdDR/rgZw/0dktJHjVkqQr\n\tA6hzILj62hNhs/odqEm7jsd3dQ=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; s=default; bh=UA3qVWykSqsUx0+x5uII2gb\n\tAIXY=; b=OOfGYVCYaWmzDLvdBmTt5aoGyou3KKwB0Ns6W/o5vzpZyIqxq7GgKrE\n\tgYQ4BQgW3NaoB/7ahz5892ouP40zcSeway9mFMON0+3vaeyxdRIU20qFASAjZtsI\n\t2xCy1vPeclf702TTP3hJKd7rPI2cbF+4mAPmSBrJxFRHcn/d3yGk=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-11.1 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2\n\tspammy=Hx-languages-length:4434, love","X-HELO":"gate.crashing.org","Date":"Wed, 6 Sep 2017 14:14:26 -0500","From":"Segher Boessenkool ","To":"Carl Love ","Cc":"gcc-patches@gcc.gnu.org, David Edelsohn ,\n\tBill Schmidt ","Subject":"Re: [PATCH,\n\trs6000] Add support for vec_xst_len_r() and vec_xl_len_r() builtins","Message-ID":"<20170906191426.GL13471@gate.crashing.org>","References":"<1504711323.18797.5.camel@us.ibm.com>","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504711323.18797.5.camel@us.ibm.com>","User-Agent":"Mutt/1.4.2.3i","X-IsSubscribed":"yes"}},{"id":1768844,"web_url":"http://patchwork.ozlabs.org/comment/1768844/","msgid":"<1505424227.12239.10.camel@us.ibm.com>","list_archive_url":null,"date":"2017-09-14T21:23:47","subject":"Re: [PATCH, rs6000 version 2] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","submitter":{"id":1003,"url":"http://patchwork.ozlabs.org/api/people/1003/","name":"Carl Love","email":"cel@us.ibm.com"},"content":"GCC maintainers:\n\nHere is an updated patch to address the comment from Segher. The one\ncomment that was not addressed was:\n\n>> +(define_insn \"altivec_lvsl_reg\"\n>> + [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n>> + (unspec:V16QI\n>> + [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n>> + UNSPEC_LVSL_REG))]\n>> + \"TARGET_ALTIVEC\"\n>> + \"lvsl %0,0,%1\"\n>> + [(set_attr \"type\" \"vecload\")])\n\nvecload isn't really the correct type for this, but I see we have the\nsame on the existing lvsl patterns (it's permute unit on p9; I expect\nthe same on p8 and older, but please check).\n\nPer our additional discussions Segher said:\n\n> You can leave it as vecload just like the other lvsl's we have, leave\n> the cleanup for a later date.\n\nI believe everything else has been addressed. The patch was retested on\npowerpc64le-unknown-linux-gnu (Power 9 LE) and\npowerpc64le-unknown-linux-gnu (Power 8 LE) without regressions.\n\nLet me know if there are additional issues that need addressing.\nThanks.\n\n Carl Love\n\n------------------------------------------------------------------------------\n\ngcc/ChangeLog:\n\n2017-09-14 Carl Love \n\n\t* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R,\n\tP9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins\n\tvector unsigned char vec_xl_len_r (unsigned char *, size_t);\n\tvoid vec_xst_len_r (vector unsigned char, unsigned char *, size_t);\n\t* config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines.\n\t* config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add\n\tdefinitions and overloading.\n\t* config/rs6000/rs6000.c (altivec_expand_builtin): Add case\n\tstatement for P9V_BUILTIN_XST_LEN_R.\n\t(altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL.\n\t* config/rs6000/vsx.md (lxvll, stxvll, xl_len_r, xst_len_r): Add\n\tdefine_expand and define_insn for the instructions and builtins.\n\t* doc/extend.texi: Update the built-in documenation file for the new\n\tbuilt-in functions.\n\t* config/rs6000/altivec.md (altivec_lvsl_reg, altivec_lvsr_reg): Add\n\tdefine_insn for the instructions\n\ngcc/testsuite/ChangeLog:\n\n2017-09-14 Carl Love \n\n\t* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file\n\tfor the new built-ins and the existing built-ins.\n---\n gcc/config/rs6000/altivec.h | 2 +\n gcc/config/rs6000/altivec.md | 18 ++\n gcc/config/rs6000/rs6000-builtin.def | 4 +\n gcc/config/rs6000/rs6000-c.c | 8 +\n gcc/config/rs6000/rs6000.c | 11 +-\n gcc/config/rs6000/vsx.md | 114 ++++++++\n gcc/doc/extend.texi | 4 +\n .../gcc.target/powerpc/builtins-5-p9-runnable.c | 309 +++++++++++++++++++++\n 8 files changed, 468 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n\ndiff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h\nindex c8e508cf0..94a4db24a 100644\n--- a/gcc/config/rs6000/altivec.h\n+++ b/gcc/config/rs6000/altivec.h\n@@ -467,6 +467,8 @@\n #ifdef _ARCH_PPC64\n #define vec_xl_len __builtin_vec_lxvl\n #define vec_xst_len __builtin_vec_stxvl\n+#define vec_xl_len_r __builtin_vec_xl_len_r\n+#define vec_xst_len_r __builtin_vec_xst_len_r\n #endif\n \n #define vec_cmpnez __builtin_vec_vcmpnez\ndiff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md\nindex 0aa1e3016..3436c0dfd 100644\n--- a/gcc/config/rs6000/altivec.md\n+++ b/gcc/config/rs6000/altivec.md\n@@ -2542,6 +2542,15 @@\n DONE;\n })\n \n+(define_insn \"altivec_lvsl_reg\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+\t(unspec:V16QI\n+\t[(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+\tUNSPEC_LVSL_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsl %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n (define_insn \"altivec_lvsl_direct\"\n [(set (match_operand:V16QI 0 \"register_operand\" \"=v\")\n \t(unspec:V16QI [(match_operand:V16QI 1 \"memory_operand\" \"Z\")]\n@@ -2574,6 +2583,15 @@\n DONE;\n })\n \n+(define_insn \"altivec_lvsr_reg\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (unspec:V16QI\n+ [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+ UNSPEC_LVSR_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsr %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n (define_insn \"altivec_lvsr_direct\"\n [(set (match_operand:V16QI 0 \"register_operand\" \"=v\")\n \t(unspec:V16QI [(match_operand:V16QI 1 \"memory_operand\" \"Z\")]\ndiff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def\nindex 850164a09..8f87ccea4 100644\n--- a/gcc/config/rs6000/rs6000-builtin.def\n+++ b/gcc/config/rs6000/rs6000-builtin.def\n@@ -2125,6 +2125,7 @@ BU_P9V_OVERLOAD_2 (VIESP,\t\"insert_exp_sp\")\n \n /* 2 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_64BIT_VSX_2 (LXVL,\t\"lxvl\",\t\tCONST,\tlxvl)\n+BU_P9V_64BIT_VSX_2 (XL_LEN_R,\t\"xl_len_r\",\tCONST, xl_len_r)\n \n BU_P9V_AV_2 (VEXTUBLX, \"vextublx\",\t\tCONST,\tvextublx)\n BU_P9V_AV_2 (VEXTUBRX, \"vextubrx\",\t\tCONST,\tvextubrx)\n@@ -2141,6 +2142,7 @@ BU_P9V_VSX_3 (VINSERT4B_DI, \"vinsert4b_di\",\tCONST,\tvinsert4b_di)\n /* 3 argument vector functions returning void, treated as SPECIAL,\n added in ISA 3.0 (power9). */\n BU_P9V_64BIT_AV_X (STXVL,\t\"stxvl\",\tMISC)\n+BU_P9V_64BIT_AV_X (XST_LEN_R,\t\"xst_len_r\",\tMISC)\n \n /* 1 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_AV_1 (VCLZLSBB, \"vclzlsbb\",\t\tCONST,\tvclzlsbb)\n@@ -2182,12 +2184,14 @@ BU_P9V_AV_P (VCMPNEZW_P,\t\"vcmpnezw_p\",\tCONST,\tvector_nez_v4si_p)\n \n /* ISA 3.0 Vector scalar overloaded 2 argument functions */\n BU_P9V_OVERLOAD_2 (LXVL,\t\"lxvl\")\n+BU_P9V_OVERLOAD_2 (XL_LEN_R,\t\"xl_len_r\")\n BU_P9V_OVERLOAD_2 (VEXTULX,\t\"vextulx\")\n BU_P9V_OVERLOAD_2 (VEXTURX,\t\"vexturx\")\n BU_P9V_OVERLOAD_2 (VEXTRACT4B,\t\"vextract4b\")\n \n /* ISA 3.0 Vector scalar overloaded 3 argument functions */\n BU_P9V_OVERLOAD_3 (STXVL,\t\"stxvl\")\n+BU_P9V_OVERLOAD_3 (XST_LEN_R,\t\"xst_len_r\")\n BU_P9V_OVERLOAD_3 (VINSERT4B,\t\"vinsert4b\")\n \n /* Overloaded CMPNE support was implemented prior to Power 9,\ndiff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c\nindex b2df850e8..2388260be 100644\n--- a/gcc/config/rs6000/rs6000-c.c\n+++ b/gcc/config/rs6000/rs6000-c.c\n@@ -4789,6 +4789,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,\n RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },\n \n+ { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,\n+ RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,\n+ RS6000_BTI_unsigned_long_long, 0 },\n+\n { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,\n RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long, 0 },\n@@ -4833,6 +4837,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n /* At an appropriate future time, add support for the\n RS6000_BTI_Float16 (exact name to be determined) type here. */\n \n+ { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,\n+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,\n+ ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},\n+\n { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,\n RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long },\ndiff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c\nindex ecdf776b9..10919edc7 100644\n--- a/gcc/config/rs6000/rs6000.c\n+++ b/gcc/config/rs6000/rs6000.c\n@@ -15546,6 +15546,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)\n case P9V_BUILTIN_STXVL:\n return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);\n \n+ case P9V_BUILTIN_XST_LEN_R:\n+ return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);\n+\n case VSX_BUILTIN_STXVD2X_V1TI:\n return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);\n case VSX_BUILTIN_STXVD2X_V2DF:\n@@ -17488,8 +17491,12 @@ altivec_init_builtins (void)\n def_builtin (\"__builtin_vec_stvrxl\", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);\n \n if (TARGET_P9_VECTOR)\n- def_builtin (\"__builtin_altivec_stxvl\", void_ftype_v16qi_pvoid_long,\n-\t\t P9V_BUILTIN_STXVL);\n+ {\n+ def_builtin (\"__builtin_altivec_stxvl\", void_ftype_v16qi_pvoid_long,\n+\t\t P9V_BUILTIN_STXVL);\n+ def_builtin (\"__builtin_xst_len_r\", void_ftype_v16qi_pvoid_long,\n+\t\t P9V_BUILTIN_XST_LEN_R);\n+ }\n \n /* Add the DST variants. */\n d = bdesc_dst;\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex 9b24c7b72..0af8e5a77 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -382,8 +382,17 @@\n UNSPEC_VSX_VTSTDC\n UNSPEC_VSX_VEC_INIT\n UNSPEC_VSX_VSIGNED2\n+\n UNSPEC_LXVL\n+ UNSPEC_LXVLL\n+ UNSPEC_LVSL_REG\n+ UNSPEC_LVSR_REG\n+ UNSPEC_SLDI\n UNSPEC_STXVL\n+ UNSPEC_STXVLL\n+ UNSPEC_XL_LEN_R\n+ UNSPEC_XST_LEN_R\n+\n UNSPEC_VCLZLSBB\n UNSPEC_VCTZLSBB\n UNSPEC_VEXTUBLX\n@@ -4352,6 +4361,87 @@\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecload\")])\n \n+;; Load VSX Vector with Length, right justified\n+(define_expand \"lxvll\"\n+ [(set (match_dup 3)\n+\t(match_operand:DI 2 \"register_operand\"))\n+ (set (match_operand:V16QI 0 \"vsx_register_operand\")\n+\t(unspec:V16QI\n+\t[(match_operand:DI 1 \"gpc_reg_operand\")\n+\t (match_dup 3)]\n+\tUNSPEC_LXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+{\n+ operands[3] = gen_reg_rtx (DImode);\n+})\n+\n+(define_insn \"sldi\"\n+ [(set (match_operand:DI 0 \"vsx_register_operand\" \"=r\")\n+\t(unspec:DI [(match_operand:DI 1 \"gpc_reg_operand\" \"r\")\n+\t\t (match_operand:DI 2 \"u6bit_cint_operand\" \"\")]\n+\t\t UNSPEC_SLDI))]\n+ \"\"\n+ \"sldi %0,%1,%2\"\n+)\n+\n+(define_insn \"*lxvll\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V16QI [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n+\t\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n+\t\t UNSPEC_LXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+ \"lxvll %x0,%1,%2;\"\n+ [(set_attr \"length\" \"4\")\n+ (set_attr \"type\" \"vecload\")])\n+\n+;; Expand for builtin xl_len_r\n+(define_expand \"xl_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (match_operand:DI 1 \"register_operand\" \"r\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"UNSPEC_XL_LEN_R\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+ /* Setup permute vector to shift right by operands[2] bytes.\n+ Note: operands[2] is between 0 and 15, adding -16 to it results\n+ in a negative value. Shifting left by a negative value results in\n+ the value being shifted right by the desired amount. */\n+ emit_insn (gen_adddi3 (tmp, operands[2], GEN_INT (-16)));\n+ emit_insn (gen_altivec_lvsl_reg (shift_mask, tmp));\n+ emit_insn (gen_sldi (operands[2], operands[2], GEN_INT (56)));\n+ emit_insn (gen_lxvll (rtx_vtmp, operands[1], operands[2]));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp,\n+\t\t\t\t\t rtx_vtmp, shift_mask));\n+ DONE;\n+})\n+\n+;; Store VSX Vector with Length, left justified\n+(define_expand \"stxvll\"\n+ [(set (match_dup 3)\n+\t(match_operand:DI 2 \"register_operand\"))\n+ (set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\"))\n+\t(unspec:V16QI [(match_operand:V16QI 0 \"vsx_register_operand\")\n+\t\t (match_dup 3)]\n+\t\t UNSPEC_STXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+{\n+ operands[3] = gen_reg_rtx (DImode);\n+})\n+\n+(define_insn \"*stxvll\"\n+ [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n+\t(unspec:V16QI\n+\t [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n+\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n+\t UNSPEC_STXVLL))]\n+ \"TARGET_P9_VECTOR && TARGET_64BIT\"\n+ \"stxvll %x0,%1,%2\"\n+ [(set_attr \"length\" \"8\")\n+ (set_attr \"type\" \"vecstore\")])\n+\n ;; Store VSX Vector with Length\n (define_expand \"stxvl\"\n [(set (match_dup 3)\n@@ -4377,6 +4467,30 @@\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecstore\")])\n \n+;; Expand for builtin xst_len_r\n+(define_expand \"xst_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n+ (match_operand:DI 1 \"register_operand\" \"r\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"UNSPEC_XST_LEN_R\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+ /* Setup permute vector to shift right by operands[2] bytes.\n+ Note: operands[2] is between 0 and 15, adding -16 to it results\n+ in a negative value. Shifting right by a negative value results in\n+ the value being shifted left by the desired amount. */\n+ emit_insn (gen_adddi3 (tmp, operands[2], GEN_INT (-16)));\n+ emit_insn (gen_altivec_lvsr_reg (shift_mask, tmp));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0],\n+\t\t\t\t\t operands[0], shift_mask));\n+ emit_insn (gen_sldi (operands[2], operands[2], GEN_INT (56)));\n+ emit_insn (gen_stxvll (rtx_vtmp, operands[1], operands[2]));\n+ DONE;\n+})\n+\n ;; Vector Compare Not Equal Byte\n (define_insn \"vcmpneb\"\n [(set (match_operand:V16QI 0 \"altivec_register_operand\" \"=v\")\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 649be015d..37fd769df 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -15631,6 +15631,8 @@ vector unsigned short vec_xl_len (unsigned short *addr, size_t len);\n vector double vec_xl_len (double *addr, size_t len);\n vector float vec_xl_len (float *addr, size_t len);\n \n+vector unsigned char vec_xl_len_r (unsigned char *addr, size_t len);\n+\n void vec_xst_len (vector signed char data, signed char *addr, size_t len);\n void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);\n void vec_xst_len (vector signed int data, signed int *addr, size_t len);\n@@ -15644,6 +15646,8 @@ void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len\n void vec_xst_len (vector double data, double *addr, size_t len);\n void vec_xst_len (vector float data, float *addr, size_t len);\n \n+void vec_xst_len_r (vector unsigned char data, unsigned char *addr, size_t len);\n+\n signed char vec_xlx (unsigned int index, vector signed char data);\n unsigned char vec_xlx (unsigned int index, vector unsigned char data);\n signed short vec_xlx (unsigned int index, vector signed short data);\ndiff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\nnew file mode 100644\nindex 000000000..ad3947196\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n@@ -0,0 +1,309 @@\n+/* { dg-do run { target { powerpc*-*-* && p9vector_hw } } } */\n+/* { dg-skip-if \"do not override -mcpu\" { powerpc*-*-* } { \"-mcpu=*\" } { \"-mcpu=power9\" } } */\n+/* { dg-options \"-mcpu=power9 -O2\" } */\n+\n+#include \n+#include \n+#include \n+#include // vector\n+\n+#define TRUE 1\n+#define FALSE 0\n+\n+#ifdef DEBUG\n+#include \n+#endif\n+\n+void abort (void);\n+\n+int result_wrong(vector unsigned char vec_expected,\n+\t\t vector unsigned char vec_actual)\n+{\n+ int i;\n+\n+ for (i=0; i<16; i++)\n+ if (vec_expected[i] != vec_actual[i])\n+ return TRUE;\n+\n+ return FALSE;\n+}\n+\n+int main() {\n+ int i, j;\n+ size_t size;\n+ unsigned char data_uc[100];\n+ vector unsigned char store_data_uc;\n+ unsigned char *address;\n+ vector unsigned char *datap;\n+ \n+ vector unsigned char vec_uc_expected1, vec_uc_expected2,\n+ vec_uc_result1, vec_uc_result2;\n+ vector int data_int;\n+ \n+ for (i=0; i<100; i++)\n+ data_uc[i] = i+1;\n+\n+ \n+ /* VEC_XL_LEN */\n+ \n+ size = 8;\n+ vec_uc_result1 = vec_xl_len (data_uc, size);\n+\n+ vec_uc_expected1 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 0, 0, 0, 0, 0, 0, 0, 0};\n+ \n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len (%d): vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\",vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xl_len (%d): vec_uc_result1[0] to vec_uc_result1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XL_LEN_R */\n+ size = 8;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){8, 7, 6, 5, 4, 3, 2, 1,\n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0,};\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+ \n+\n+ size = 4;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 4, 3, 2, 1, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ size = 2;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XST_LEN */\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+ \n+ address = &vec_uc_result2[0];\n+ vec_xst_len (store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+\n+ address = &vec_uc_result2[0];\n+\n+ vec_xst_len (store_data_uc, address, size);\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ /* VEC_XST_LEN_R */\n+ vec_uc_expected1 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ vec_uc_expected1 = (vector unsigned char){ 14, 13, 12, 11, 10, 9, 8, 7,\n+ 6, 5, 4, 3, 2, 1, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462179-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"me/wFSbS\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtWkM0h7kz9s78\n\tfor ;\n\tFri, 15 Sep 2017 07:24:09 +1000 (AEST)","(qmail 43389 invoked by alias); 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lvsl can target only the VR regs, not\nall VSR regs.\n\n> +;; Load VSX Vector with Length, right justified\n> +(define_expand \"lxvll\"\n> + [(set (match_dup 3)\n> +\t(match_operand:DI 2 \"register_operand\"))\n> + (set (match_operand:V16QI 0 \"vsx_register_operand\")\n> +\t(unspec:V16QI\n> +\t[(match_operand:DI 1 \"gpc_reg_operand\")\n> +\t (match_dup 3)]\n> +\tUNSPEC_LXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> +{\n> + operands[3] = gen_reg_rtx (DImode);\n> +})\n\nI don't think you need to copy operands[2] to a temporary here, see below.\n\nWhy does this require TARGET_64BIT?\n\n> +(define_insn \"sldi\"\n> + [(set (match_operand:DI 0 \"vsx_register_operand\" \"=r\")\n> +\t(unspec:DI [(match_operand:DI 1 \"gpc_reg_operand\" \"r\")\n> +\t\t (match_operand:DI 2 \"u6bit_cint_operand\" \"\")]\n> +\t\t UNSPEC_SLDI))]\n> + \"\"\n> + \"sldi %0,%1,%2\"\n> +)\n\nAs we discussed, you can just use ashldi3.\n\n> +(define_insn \"*lxvll\"\n> + [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n> +\t(unspec:V16QI [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n> +\t\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n> +\t\t UNSPEC_LXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> + \"lxvll %x0,%1,%2;\"\n> + [(set_attr \"length\" \"4\")\n> + (set_attr \"type\" \"vecload\")])\n\nWhy \"+r\"? The instruction doesn't write to that reg. A leftover from\nan earlier version of the patch, I guess.\n\nNo \";\" at the end of pattern strings please.\n\nLength 4 is the default, just leave it out.\n\n> +;; Expand for builtin xl_len_r\n> +(define_expand \"xl_len_r\"\n> + [(match_operand:V16QI 0 \"vsx_register_operand\" \"=v\")\n> + (match_operand:DI 1 \"register_operand\" \"r\")\n> + (match_operand:DI 2 \"register_operand\" \"r\")]\n> + \"UNSPEC_XL_LEN_R\"\n\nExpanders don't need constraints; just leave them out :-)\n\n> +{\n> + rtx shift_mask = gen_reg_rtx (V16QImode);\n> + rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n> + rtx tmp = gen_reg_rtx (DImode);\n> +\n> + /* Setup permute vector to shift right by operands[2] bytes.\n> + Note: operands[2] is between 0 and 15, adding -16 to it results\n> + in a negative value. Shifting left by a negative value results in\n> + the value being shifted right by the desired amount. */\n> + emit_insn (gen_adddi3 (tmp, operands[2], GEN_INT (-16)));\n> + emit_insn (gen_altivec_lvsl_reg (shift_mask, tmp));\n\nSince lvsl looks only at the low four bits, adding -16 does nothing for it.\n\n> + emit_insn (gen_sldi (operands[2], operands[2], GEN_INT (56)));\n\nPlease use a new temporary instead of reusing operands[2]; this gives the\nregister allocator more freedom.\n\n> +(define_insn \"*stxvll\"\n> + [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n> +\t(unspec:V16QI\n> +\t [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n> +\t (match_operand:DI 2 \"register_operand\" \"+r\")]\n> +\t UNSPEC_STXVLL))]\n> + \"TARGET_P9_VECTOR && TARGET_64BIT\"\n> + \"stxvll %x0,%1,%2\"\n> + [(set_attr \"length\" \"8\")\n> + (set_attr \"type\" \"vecstore\")])\n\nThat's the wrong length now (just a single insn; doesn't need a length\nattribute).\n\nMany of these comments apply to multiple places, please check all.\n\nThanks,\n\n\nSegher","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-0.3 required=5.0 tests=AWL, BAYES_00,\n\tRP_MATCHES_RCVD,\n\tUNSUBSCRIBE_BODY autolearn=no version=3.3.2 spammy=love","X-HELO":"gate.crashing.org","Date":"Fri, 15 Sep 2017 10:42:13 -0500","From":"Segher Boessenkool ","To":"Carl Love ","Cc":"gcc-patches@gcc.gnu.org, David Edelsohn ,\n\tBill Schmidt ","Subject":"Re: [PATCH, rs6000 version 2] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","Message-ID":"<20170915154212.GF8421@gate.crashing.org>","References":"<1504711323.18797.5.camel@us.ibm.com>\n\t<20170906191426.GL13471@gate.crashing.org>\n\t<1505424227.12239.10.camel@us.ibm.com>","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1505424227.12239.10.camel@us.ibm.com>","User-Agent":"Mutt/1.4.2.3i","X-IsSubscribed":"yes"}},{"id":1770406,"web_url":"http://patchwork.ozlabs.org/comment/1770406/","msgid":"<1505759467.12239.26.camel@us.ibm.com>","list_archive_url":null,"date":"2017-09-18T18:31:07","subject":"Re: [PATCH, rs6000 version 3] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","submitter":{"id":1003,"url":"http://patchwork.ozlabs.org/api/people/1003/","name":"Carl Love","email":"cel@us.ibm.com"},"content":"GCC maintianers:\n\nAddressed the comments from Segher about copying operands in\ndefine_expand lxvll and stxvll. Added new temp for the output of the\nsldi instructions to give the allocator the freedom to select the\nregisters. Removed constraints in the expanders. Cleaned up issues\nleft over from the previous patch version. Removed length attributes\nthat are now 4 rather then 8.\n\nTested on \npowerpc64le-unknown-linux-gnu (Power 9 LE),\npowerpc64le-unknown-linux-gnu (Power 8 LE) and\npowerpc64le-unknown-linux-gnu (Power 8 BE) without regressions.\n\nPlease let me know if there are any additional issues to address.\n\n\n----------------------------------------------------------------------------\n\n2017-09-18 Carl Love \n\n\t* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R,\n\tP9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins\n\tvector unsigned char vec_xl_len_r (unsigned char *, size_t);\n\tvoid vec_xst_len_r (vector unsigned char, unsigned char *, size_t);\n\t* config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines.\n\t* config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add\n\tdefinitions and overloading.\n\t* config/rs6000/rs6000.c (altivec_expand_builtin): Add case\n\tstatement for P9V_BUILTIN_XST_LEN_R.\n\t(altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL.\n\t* config/rs6000/vsx.md (lxvll, stxvll, xl_len_r, xst_len_r): Add\n\tdefine_expand and define_insn for the instructions and builtins.\n\t* doc/extend.texi: Update the built-in documentation file for the new\n\tbuilt-in functions.\n\t* config/rs6000/altivec.md (altivec_lvsl_reg, altivec_lvsr_reg): Add\n\tdefine_insn for the instructions\n\ngcc/testsuite/ChangeLog:\n\n2017-09-18 Carl Love \n\n\t* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file\n\tfor the new built-ins and the existing built-ins.\n---\n gcc/config/rs6000/altivec.h | 2 +\n gcc/config/rs6000/altivec.md | 20 +-\n gcc/config/rs6000/rs6000-builtin.def | 4 +\n gcc/config/rs6000/rs6000-c.c | 8 +\n gcc/config/rs6000/rs6000.c | 11 +-\n gcc/config/rs6000/vsx.md | 64 +++++\n gcc/doc/extend.texi | 4 +\n .../gcc.target/powerpc/builtins-5-p9-runnable.c | 309 +++++++++++++++++++++\n 8 files changed, 419 insertions(+), 3 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n\ndiff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h\nindex c8e508cf0..94a4db24a 100644\n--- a/gcc/config/rs6000/altivec.h\n+++ b/gcc/config/rs6000/altivec.h\n@@ -467,6 +467,8 @@\n #ifdef _ARCH_PPC64\n #define vec_xl_len __builtin_vec_lxvl\n #define vec_xst_len __builtin_vec_stxvl\n+#define vec_xl_len_r __builtin_vec_xl_len_r\n+#define vec_xst_len_r __builtin_vec_xst_len_r\n #endif\n \n #define vec_cmpnez __builtin_vec_vcmpnez\ndiff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md\nindex 0aa1e3016..a01720545 100644\n--- a/gcc/config/rs6000/altivec.md\n+++ b/gcc/config/rs6000/altivec.md\n@@ -2542,6 +2542,15 @@\n DONE;\n })\n \n+(define_insn \"altivec_lvsl_reg\"\n+ [(set (match_operand:V16QI 0 \"altivec_register_operand\" \"=v\")\n+\t(unspec:V16QI\n+\t[(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+\tUNSPEC_LVSL_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsl %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n (define_insn \"altivec_lvsl_direct\"\n [(set (match_operand:V16QI 0 \"register_operand\" \"=v\")\n \t(unspec:V16QI [(match_operand:V16QI 1 \"memory_operand\" \"Z\")]\n@@ -2551,7 +2560,7 @@\n [(set_attr \"type\" \"vecload\")])\n \n (define_expand \"altivec_lvsr\"\n- [(use (match_operand:V16QI 0 \"register_operand\" \"\"))\n+ [(use (match_operand:V16QI 0 \"altivec_register_operand\" \"\"))\n (use (match_operand:V16QI 1 \"memory_operand\" \"\"))]\n \"TARGET_ALTIVEC\"\n {\n@@ -2574,6 +2583,15 @@\n DONE;\n })\n \n+(define_insn \"altivec_lvsr_reg\"\n+ [(set (match_operand:V16QI 0 \"altivec_register_operand\" \"=v\")\n+ (unspec:V16QI\n+ [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")]\n+ UNSPEC_LVSR_REG))]\n+ \"TARGET_ALTIVEC\"\n+ \"lvsr %0,0,%1\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n (define_insn \"altivec_lvsr_direct\"\n [(set (match_operand:V16QI 0 \"register_operand\" \"=v\")\n \t(unspec:V16QI [(match_operand:V16QI 1 \"memory_operand\" \"Z\")]\ndiff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def\nindex 850164a09..8f87ccea4 100644\n--- a/gcc/config/rs6000/rs6000-builtin.def\n+++ b/gcc/config/rs6000/rs6000-builtin.def\n@@ -2125,6 +2125,7 @@ BU_P9V_OVERLOAD_2 (VIESP,\t\"insert_exp_sp\")\n \n /* 2 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_64BIT_VSX_2 (LXVL,\t\"lxvl\",\t\tCONST,\tlxvl)\n+BU_P9V_64BIT_VSX_2 (XL_LEN_R,\t\"xl_len_r\",\tCONST, xl_len_r)\n \n BU_P9V_AV_2 (VEXTUBLX, \"vextublx\",\t\tCONST,\tvextublx)\n BU_P9V_AV_2 (VEXTUBRX, \"vextubrx\",\t\tCONST,\tvextubrx)\n@@ -2141,6 +2142,7 @@ BU_P9V_VSX_3 (VINSERT4B_DI, \"vinsert4b_di\",\tCONST,\tvinsert4b_di)\n /* 3 argument vector functions returning void, treated as SPECIAL,\n added in ISA 3.0 (power9). */\n BU_P9V_64BIT_AV_X (STXVL,\t\"stxvl\",\tMISC)\n+BU_P9V_64BIT_AV_X (XST_LEN_R,\t\"xst_len_r\",\tMISC)\n \n /* 1 argument vector functions added in ISA 3.0 (power9). */\n BU_P9V_AV_1 (VCLZLSBB, \"vclzlsbb\",\t\tCONST,\tvclzlsbb)\n@@ -2182,12 +2184,14 @@ BU_P9V_AV_P (VCMPNEZW_P,\t\"vcmpnezw_p\",\tCONST,\tvector_nez_v4si_p)\n \n /* ISA 3.0 Vector scalar overloaded 2 argument functions */\n BU_P9V_OVERLOAD_2 (LXVL,\t\"lxvl\")\n+BU_P9V_OVERLOAD_2 (XL_LEN_R,\t\"xl_len_r\")\n BU_P9V_OVERLOAD_2 (VEXTULX,\t\"vextulx\")\n BU_P9V_OVERLOAD_2 (VEXTURX,\t\"vexturx\")\n BU_P9V_OVERLOAD_2 (VEXTRACT4B,\t\"vextract4b\")\n \n /* ISA 3.0 Vector scalar overloaded 3 argument functions */\n BU_P9V_OVERLOAD_3 (STXVL,\t\"stxvl\")\n+BU_P9V_OVERLOAD_3 (XST_LEN_R,\t\"xst_len_r\")\n BU_P9V_OVERLOAD_3 (VINSERT4B,\t\"vinsert4b\")\n \n /* Overloaded CMPNE support was implemented prior to Power 9,\ndiff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c\nindex b2df850e8..2388260be 100644\n--- a/gcc/config/rs6000/rs6000-c.c\n+++ b/gcc/config/rs6000/rs6000-c.c\n@@ -4789,6 +4789,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,\n RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },\n \n+ { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,\n+ RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,\n+ RS6000_BTI_unsigned_long_long, 0 },\n+\n { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,\n RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long, 0 },\n@@ -4833,6 +4837,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {\n /* At an appropriate future time, add support for the\n RS6000_BTI_Float16 (exact name to be determined) type here. */\n \n+ { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,\n+ RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,\n+ ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},\n+\n { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,\n RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,\n RS6000_BTI_unsigned_long_long },\ndiff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c\nindex ecdf776b9..10919edc7 100644\n--- a/gcc/config/rs6000/rs6000.c\n+++ b/gcc/config/rs6000/rs6000.c\n@@ -15546,6 +15546,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)\n case P9V_BUILTIN_STXVL:\n return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);\n \n+ case P9V_BUILTIN_XST_LEN_R:\n+ return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);\n+\n case VSX_BUILTIN_STXVD2X_V1TI:\n return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);\n case VSX_BUILTIN_STXVD2X_V2DF:\n@@ -17488,8 +17491,12 @@ altivec_init_builtins (void)\n def_builtin (\"__builtin_vec_stvrxl\", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);\n \n if (TARGET_P9_VECTOR)\n- def_builtin (\"__builtin_altivec_stxvl\", void_ftype_v16qi_pvoid_long,\n-\t\t P9V_BUILTIN_STXVL);\n+ {\n+ def_builtin (\"__builtin_altivec_stxvl\", void_ftype_v16qi_pvoid_long,\n+\t\t P9V_BUILTIN_STXVL);\n+ def_builtin (\"__builtin_xst_len_r\", void_ftype_v16qi_pvoid_long,\n+\t\t P9V_BUILTIN_XST_LEN_R);\n+ }\n \n /* Add the DST variants. */\n d = bdesc_dst;\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex 9b24c7b72..c5e56e96e 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -382,8 +382,16 @@\n UNSPEC_VSX_VTSTDC\n UNSPEC_VSX_VEC_INIT\n UNSPEC_VSX_VSIGNED2\n+\n UNSPEC_LXVL\n+ UNSPEC_LXVLL\n+ UNSPEC_LVSL_REG\n+ UNSPEC_LVSR_REG\n UNSPEC_STXVL\n+ UNSPEC_STXVLL\n+ UNSPEC_XL_LEN_R\n+ UNSPEC_XST_LEN_R\n+\n UNSPEC_VCLZLSBB\n UNSPEC_VCTZLSBB\n UNSPEC_VEXTUBLX\n@@ -4352,6 +4360,43 @@\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecload\")])\n \n+(define_insn \"lxvll\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V16QI [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n+\t\t (match_operand:DI 2 \"register_operand\" \"r\")]\n+\t\t UNSPEC_LXVLL))]\n+ \"TARGET_P9_VECTOR\"\n+ \"lxvll %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n+;; Expand for builtin xl_len_r\n+(define_expand \"xl_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+ (match_operand:DI 1 \"register_operand\" \"b\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+ emit_insn (gen_altivec_lvsl_reg (shift_mask, operands[2]));\n+ emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));\n+ emit_insn (gen_lxvll (rtx_vtmp, operands[1], tmp));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp, rtx_vtmp,\n+\t shift_mask));\n+ DONE;\n+})\n+\n+(define_insn \"stxvll\"\n+ [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n+\t(unspec:V16QI [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n+\t\t (match_operand:DI 2 \"register_operand\" \"r\")]\n+\t UNSPEC_STXVLL))]\n+ \"TARGET_P9_VECTOR\"\n+ \"stxvll %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecstore\")])\n+\n ;; Store VSX Vector with Length\n (define_expand \"stxvl\"\n [(set (match_dup 3)\n@@ -4377,6 +4422,25 @@\n [(set_attr \"length\" \"8\")\n (set_attr \"type\" \"vecstore\")])\n \n+;; Expand for builtin xst_len_r\n+(define_expand \"xst_len_r\"\n+ [(match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+ (match_operand:DI 1 \"register_operand\" \"b\")\n+ (match_operand:DI 2 \"register_operand\" \"r\")]\n+ \"UNSPEC_XST_LEN_R\"\n+{\n+ rtx shift_mask = gen_reg_rtx (V16QImode);\n+ rtx rtx_vtmp = gen_reg_rtx (V16QImode);\n+ rtx tmp = gen_reg_rtx (DImode);\n+\n+ emit_insn (gen_altivec_lvsr_reg (shift_mask, operands[2]));\n+ emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0], operands[0],\n+\t shift_mask));\n+ emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));\n+ emit_insn (gen_stxvll (rtx_vtmp, operands[1], tmp));\n+ DONE;\n+})\n+\n ;; Vector Compare Not Equal Byte\n (define_insn \"vcmpneb\"\n [(set (match_operand:V16QI 0 \"altivec_register_operand\" \"=v\")\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 649be015d..37fd769df 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -15631,6 +15631,8 @@ vector unsigned short vec_xl_len (unsigned short *addr, size_t len);\n vector double vec_xl_len (double *addr, size_t len);\n vector float vec_xl_len (float *addr, size_t len);\n \n+vector unsigned char vec_xl_len_r (unsigned char *addr, size_t len);\n+\n void vec_xst_len (vector signed char data, signed char *addr, size_t len);\n void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);\n void vec_xst_len (vector signed int data, signed int *addr, size_t len);\n@@ -15644,6 +15646,8 @@ void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len\n void vec_xst_len (vector double data, double *addr, size_t len);\n void vec_xst_len (vector float data, float *addr, size_t len);\n \n+void vec_xst_len_r (vector unsigned char data, unsigned char *addr, size_t len);\n+\n signed char vec_xlx (unsigned int index, vector signed char data);\n unsigned char vec_xlx (unsigned int index, vector unsigned char data);\n signed short vec_xlx (unsigned int index, vector signed short data);\ndiff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\nnew file mode 100644\nindex 000000000..ad3947196\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c\n@@ -0,0 +1,309 @@\n+/* { dg-do run { target { powerpc*-*-* && p9vector_hw } } } */\n+/* { dg-skip-if \"do not override -mcpu\" { powerpc*-*-* } { \"-mcpu=*\" } { \"-mcpu=power9\" } } */\n+/* { dg-options \"-mcpu=power9 -O2\" } */\n+\n+#include \n+#include \n+#include \n+#include // vector\n+\n+#define TRUE 1\n+#define FALSE 0\n+\n+#ifdef DEBUG\n+#include \n+#endif\n+\n+void abort (void);\n+\n+int result_wrong(vector unsigned char vec_expected,\n+\t\t vector unsigned char vec_actual)\n+{\n+ int i;\n+\n+ for (i=0; i<16; i++)\n+ if (vec_expected[i] != vec_actual[i])\n+ return TRUE;\n+\n+ return FALSE;\n+}\n+\n+int main() {\n+ int i, j;\n+ size_t size;\n+ unsigned char data_uc[100];\n+ vector unsigned char store_data_uc;\n+ unsigned char *address;\n+ vector unsigned char *datap;\n+ \n+ vector unsigned char vec_uc_expected1, vec_uc_expected2,\n+ vec_uc_result1, vec_uc_result2;\n+ vector int data_int;\n+ \n+ for (i=0; i<100; i++)\n+ data_uc[i] = i+1;\n+\n+ \n+ /* VEC_XL_LEN */\n+ \n+ size = 8;\n+ vec_uc_result1 = vec_xl_len (data_uc, size);\n+\n+ vec_uc_expected1 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 0, 0, 0, 0, 0, 0, 0, 0};\n+ \n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len (%d): vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\",vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xl_len (%d): vec_uc_result1[0] to vec_uc_result1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XL_LEN_R */\n+ size = 8;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){8, 7, 6, 5, 4, 3, 2, 1,\n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0,};\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+ \n+\n+ size = 4;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 4, 3, 2, 1, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ size = 2;\n+ vec_uc_result2 = vec_xl_len_r(data_uc, size);\n+\n+ vec_uc_expected2 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xl_len_r(%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ /* VEC_XST_LEN */\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+ \n+ address = &vec_uc_result2[0];\n+ vec_xst_len (store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ vec_uc_expected2 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result2[i] = 0;\n+\n+ address = &vec_uc_result2[0];\n+\n+ vec_xst_len (store_data_uc, address, size);\n+ \n+ if (result_wrong (vec_uc_expected2, vec_uc_result2))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\\n\",\n+\t size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result2[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+ /* VEC_XST_LEN_R */\n+ vec_uc_expected1 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 2;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected1[0] to vec_uc_expected1[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected1[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+\n+\n+ vec_uc_expected1 = (vector unsigned char){ 14, 13, 12, 11, 10, 9, 8, 7,\n+ 6, 5, 4, 3, 2, 1, 0, 0 };\n+ store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8,\n+\t\t\t\t\t 9, 10, 11, 12, 13, 14, 15, 16 };\n+ vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, \n+\t\t\t\t\t 0, 0, 0, 0, 0, 0, 0, 0 };\n+\n+ size = 14;\n+\n+ for (i=0; i<16; i++)\n+ vec_uc_result1[i] = 0;\n+\n+ address = &vec_uc_result1[0];\n+\n+ vec_xst_len_r(store_data_uc, address, size);\n+\n+ if (result_wrong (vec_uc_expected1, vec_uc_result1))\n+ {\n+#ifdef DEBUG\n+ printf(\"Error: result does not match expected result\\n\");\n+ printf(\"vec_xst_len_r(%d) vec_uc_expected2[0] to vec_uc_expected2[15]\\n\",\n+\t size);\n+ \n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_expected2[i]);\n+\n+ printf(\"\\nvec_xst_len_r(%d) result[0] to result[15]\\n\", size);\n+\n+ for (i=0; i<16; i++)\n+\t printf(\" %d,\", vec_uc_result1[i]);\n+\n+ printf(\"\\n\\n\");\n+#else\n+ abort();\n+#endif\n+ }\n+}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462426-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"WYqdgAaw\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwvjG2ggnz9s7p\n\tfor ;\n\tTue, 19 Sep 2017 04:31:30 +1000 (AEST)","(qmail 53666 invoked by alias); 18 Sep 2017 18:31:21 -0000","(qmail 53629 invoked by uid 89); 18 Sep 2017 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Violators will be prosecuted;\n\tMon, 18 Sep 2017 12:31:09 -0600","from b03ledav006.gho.boulder.ibm.com\n\t(b03ledav006.gho.boulder.ibm.com [9.17.130.237])\tby\n\tb03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0)\n\twith ESMTP id v8IIV88u25362652; Mon, 18 Sep 2017 11:31:08 -0700","from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1])\tby\n\tIMSVA (Postfix) with ESMTP id 96FE9C603E;\n\tMon, 18 Sep 2017 12:31:08 -0600 (MDT)","from oc3304648336.ibm.com (unknown [9.70.82.190])\tby\n\tb03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP id\n\t36564C6037; Mon, 18 Sep 2017 12:31:08 -0600 (MDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:to:cc:date:in-reply-to:references:content-type\n\t:mime-version:content-transfer-encoding:message-id; q=dns; s=\n\tdefault; b=IGT270PlOu/AeHEQWjhYQlYySWLTyMIbAWvSc8d2v2wDLXdKVHf09\n\tRwSl9td632ozTp3RisF8AnJUMy55NH9kQhURdNq9kbXeGvq/TWPqnrNSZYayMqOI\n\t0aDCVR/rwHyQQBQd4I28CwAUYimAjMeTCztdHFsk59hmk5zoURbys4=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:to:cc:date:in-reply-to:references:content-type\n\t:mime-version:content-transfer-encoding:message-id; s=default;\n\tbh=Lm/Ij9ejI6lmMy+zO7f3Vo6+Lig=; b=WYqdgAawPYl1a5FJRr1E1wclUYsj\n\tI6uSh8CR4vuJg5l0JztiWcyXU4xczS1nnT/++CofHcjR2LbDMgPfvuLJX/txW5sg\n\tG2MDjX6yaGznLzc1n1FNJOe3CMG0moEalxad55suv1FBWGTw9PsEXpZ+t7euHCo4\n\t4qQaM+VVFv//KYk=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-27.6 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"mx0a-001b2d01.pphosted.com","Subject":"Re: [PATCH, rs6000 version 3] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","From":"Carl Love ","To":"Segher Boessenkool ","Cc":"gcc-patches@gcc.gnu.org, David Edelsohn ,\n\tBill Schmidt ","Date":"Mon, 18 Sep 2017 11:31:07 -0700","In-Reply-To":"<1505424227.12239.10.camel@us.ibm.com>","References":"<1504711323.18797.5.camel@us.ibm.com>\t\n\t<20170906191426.GL13471@gate.crashing.org>\t\n\t<1505424227.12239.10.camel@us.ibm.com>","Content-Type":"text/plain; charset=\"UTF-8\"","Mime-Version":"1.0","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","x-cbid":"17091818-8235-0000-0000-00000C49C9F2","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007757; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000230; SDB=6.00918905; UDB=6.00461634;\n\tIPR=6.00699132; BA=6.00005595; NDR=6.00000001; ZLA=6.00000005;\n\tZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000;\n\tZU=6.00000002; MB=3.00017198; XFM=3.00000015;\n\tUTC=2017-09-18 18:31:09","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17091818-8236-0000-0000-00003DB2E476","Message-Id":"<1505759467.12239.26.camel@us.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-18_07:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0 malwarescore=0 phishscore=0\n\tadultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709180261","X-IsSubscribed":"yes"}},{"id":1773914,"web_url":"http://patchwork.ozlabs.org/comment/1773914/","msgid":"<20170922221618.GB8421@gate.crashing.org>","list_archive_url":null,"date":"2017-09-22T22:16:19","subject":"Re: [PATCH, rs6000 version 3] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","submitter":{"id":134,"url":"http://patchwork.ozlabs.org/api/people/134/","name":"Segher Boessenkool","email":"segher@kernel.crashing.org"},"content":"Hi Carl,\n\nOn Mon, Sep 18, 2017 at 11:31:07AM -0700, Carl Love wrote:\n> \t* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file\n> \tfor the new built-ins and the existing built-ins.\n\nTypo (\"runable\").\n\n> (define_expand \"altivec_lvsr\"\n> - [(use (match_operand:V16QI 0 \"register_operand\" \"\"))\n> + [(use (match_operand:V16QI 0 \"altivec_register_operand\" \"\"))\n> (use (match_operand:V16QI 1 \"memory_operand\" \"\"))]\n\nEmpty constraint strings in define_expand is the default, just leave\nthem out.\n\n> +;; Expand for builtin xl_len_r\n> +(define_expand \"xl_len_r\"\n> + [(match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n> + (match_operand:DI 1 \"register_operand\" \"b\")\n> + (match_operand:DI 2 \"register_operand\" \"r\")]\n> + \"\"\n\nNon-empty constraints in an expander do not really make sense either :-)\n\nAll the rest looks fine. Please fix up the expanders and commit.\n\nThanks!\n\n\nSegher","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462813-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"VeGvpmZZ\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzSWD6s8Gz9sxR\n\tfor ;\n\tSat, 23 Sep 2017 08:16:37 +1000 (AEST)","(qmail 70388 invoked by alias); 22 Sep 2017 22:16:29 -0000","(qmail 70378 invoked by uid 89); 22 Sep 2017 22:16:29 -0000","from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by\n\tsourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tFri, 22 Sep 2017 22:16:28 +0000","from gate.crashing.org (localhost.localdomain [127.0.0.1])\tby\n\tgate.crashing.org (8.14.1/8.13.8) with ESMTP id\n\tv8MMGMWN023425; Fri, 22 Sep 2017 17:16:23 -0500","(from segher@localhost)\tby gate.crashing.org\n\t(8.14.1/8.14.1/Submit) id v8MMGJT4023417;\n\tFri, 22 Sep 2017 17:16:19 -0500"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; q=dns; s=default; b=CudkQF8nCzbEnrGsE\n\tGf1okZbAOfM/WfMp9vxP/LywOvEshN1mg/YzaqaXZX10sbLhl3ze+Q1xGucY4RGp\n\tNO9ns1bjk3fBuaYoCbam/KLYBT07YMwUbYtGGfEp62QJ97zhOJPcObf9OaHHN3p2\n\th2g9BebS9J0UMMx6fmAIXDyw4I=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:references:mime-version\n\t:content-type:in-reply-to; s=default; bh=FJB/X4Sg+dpmiv9VRnty4AT\n\tLWRQ=; b=VeGvpmZZNcX/gMnb98jHjM16UOTN7jTSrBo7gTc5eDAn4Zvlv37vIXO\n\tB80EMBZjfVal6bm3rCIhxSnyObOl3sIq2kdXN97xpFnjSm+vBl2Te7zhF38wy6R2\n\tTYQHBbUlsM1kZLldcLIp2wks+O8ojoo/VaXhA1nHXYqTBqqJCDQk=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-2.1 required=5.0 tests=AWL, BAYES_00,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=love","X-HELO":"gate.crashing.org","Date":"Fri, 22 Sep 2017 17:16:19 -0500","From":"Segher Boessenkool ","To":"Carl Love ","Cc":"gcc-patches@gcc.gnu.org, David Edelsohn ,\n\tBill Schmidt ","Subject":"Re: [PATCH, rs6000 version 3] Add support for vec_xst_len_r() and\n\tvec_xl_len_r() builtins","Message-ID":"<20170922221618.GB8421@gate.crashing.org>","References":"<1504711323.18797.5.camel@us.ibm.com>\n\t<20170906191426.GL13471@gate.crashing.org>\n\t<1505424227.12239.10.camel@us.ibm.com>\n\t<1505759467.12239.26.camel@us.ibm.com>","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1505759467.12239.26.camel@us.ibm.com>","User-Agent":"Mutt/1.4.2.3i","X-IsSubscribed":"yes"}}]