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GET /api/patches/810075/?format=api
{ "id": 810075, "url": "http://patchwork.ozlabs.org/api/patches/810075/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170905103008.3099-2-wenyou.yang@microchip.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170905103008.3099-2-wenyou.yang@microchip.com>", "list_archive_url": null, "date": "2017-09-05T10:30:07", "name": "[U-Boot,1/2] clk: at91: utmi: Set the reference clock frequency", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "ef5832b7dfd389f38c2bb6eb91614ad66507c208", "submitter": { "id": 69532, "url": "http://patchwork.ozlabs.org/api/people/69532/?format=api", "name": "Wenyou Yang", "email": "Wenyou.Yang@microchip.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170905103008.3099-2-wenyou.yang@microchip.com/mbox/", "series": [ { "id": 1547, "url": "http://patchwork.ozlabs.org/api/series/1547/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1547", "date": "2017-09-05T10:30:06", "name": "clk: at91: utmi: Fix to set the main clock", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1547/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810075/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810075/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmjm63rvvz9s71\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 20:35:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 4A28DC21FC1; Tue, 5 Sep 2017 10:35:05 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 87C40C21D8D;\n\tTue, 5 Sep 2017 10:35:02 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 55D7DC21FAA; Tue, 5 Sep 2017 10:34:46 +0000 (UTC)", "from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.242])\n\tby lists.denx.de (Postfix) with ESMTPS id CAAB7C21F25\n\tfor <u-boot@lists.denx.de>; Tue, 5 Sep 2017 10:34:42 +0000 (UTC)", "from apsmtp01.atmel.com (10.168.254.31) by eusmtp01.atmel.com\n\t(10.145.145.30) with Microsoft SMTP Server id 14.3.235.1;\n\tTue, 5 Sep 2017 12:33:59 +0200", "from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com\n\t(10.168.254.31) with Microsoft SMTP Server id 14.3.235.1;\n\tTue, 5 Sep 2017 18:38:18 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "Wenyou Yang <wenyou.yang@microchip.com>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Tue, 5 Sep 2017 18:30:07 +0800", "Message-ID": "<20170905103008.3099-2-wenyou.yang@microchip.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170905103008.3099-1-wenyou.yang@microchip.com>", "References": "<20170905103008.3099-1-wenyou.yang@microchip.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, Stephen Warren <swarren@nvidia.com>", "Subject": "[U-Boot] [PATCH 1/2] clk: at91: utmi: Set the reference clock\n\tfrequency", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "By default, it is assumed that the UTMI clock is generated from\na 12 MHz reference clock (MAINCK). If it's not the case, the FREQ\nfield of the SFR_UTMICKTRIM has to be updated to generate the UTMI\nclock in the proper way.\n\nThe UTMI clock has a fixed rate of 480 MHz. In fact, there is no\nmultiplier we can configure. The multiplier is managed internally,\ndepending on the reference clock frequency, to achieve the target\nof 480 MHz.\n\nThe patch is cloned from the patch of mailing-list:\n\t[PATCH v2] clk: at91: utmi: set the mainck rate\n\nSigned-off-by: Wenyou Yang <wenyou.yang@microchip.com>\n---\n\n arch/arm/mach-at91/include/mach/sama5_sfr.h | 5 ++\n drivers/clk/at91/Kconfig | 4 ++\n drivers/clk/at91/clk-utmi.c | 77 ++++++++++++++++++++++++++++-\n drivers/clk/at91/pmc.h | 3 ++\n 4 files changed, 87 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h\nindex b805a2c934..965631aad7 100644\n--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h\n+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h\n@@ -28,6 +28,9 @@ struct atmel_sfr {\n \tu32 l2cc_hramc;\t/* 0x58 */\n };\n \n+/* Register Mapping*/\n+#define AT91_SFR_UTMICKTRIM\t0x30\t/* UTMI Clock Trimming Register */\n+\n /* Bit field in DDRCFG */\n #define ATMEL_SFR_DDRCFG_FDQIEN\t\t0x00010000\n #define ATMEL_SFR_DDRCFG_FDQSIEN\t0x00020000\n@@ -56,6 +59,8 @@ struct atmel_sfr {\n #define AT91_SFR_EBICFG_SCH1_OFF\t\t(0x0 << 12)\n #define AT91_SFR_EBICFG_SCH1_ON\t\t\t(0x1 << 12)\n \n+#define AT91_UTMICKTRIM_FREQ\t\tGENMASK(1, 0)\n+\n /* Bit field in AICREDIR */\n #define ATMEL_SFR_AICREDIR_NSAIC\t0x00000001\n \ndiff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig\nindex 904ed48e51..2f112afa31 100644\n--- a/drivers/clk/at91/Kconfig\n+++ b/drivers/clk/at91/Kconfig\n@@ -15,6 +15,10 @@ config CLK_AT91\n config AT91_UTMI\n \tbool \"Support UTMI PLL Clock\"\n \tdepends on CLK_AT91\n+\tselect REGMAP\n+\tselect SPL_REGMAP\n+\tselect SYSCON\n+\tselect SPL_SYSCON\n \thelp\n \t This option is used to enable the AT91 UTMI PLL clock\n \t driver. It is the clock provider of USB, and UPLLCK is the\ndiff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c\nindex af5362da42..875bf293f9 100644\n--- a/drivers/clk/at91/clk-utmi.c\n+++ b/drivers/clk/at91/clk-utmi.c\n@@ -8,23 +8,80 @@\n #include <common.h>\n #include <clk-uclass.h>\n #include <dm.h>\n+#include <syscon.h>\n #include <linux/io.h>\n #include <mach/at91_pmc.h>\n+#include <mach/sama5_sfr.h>\n #include \"pmc.h\"\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-#define UTMI_FIXED_MUL\t\t40\n+/*\n+ * The purpose of this clock is to generate a 480 MHz signal. A different\n+ * rate can't be configured.\n+ */\n+#define UTMI_RATE\t480000000\n \n static int utmi_clk_enable(struct clk *clk)\n {\n \tstruct pmc_platdata *plat = dev_get_platdata(clk->dev);\n \tstruct at91_pmc *pmc = plat->reg_base;\n+\tstruct clk clk_dev;\n+\tulong clk_rate;\n+\tu32 utmi_ref_clk_freq;\n \tu32 tmp;\n+\tint err;\n \n \tif (readl(&pmc->sr) & AT91_PMC_LOCKU)\n \t\treturn 0;\n \n+\t/*\n+\t * If mainck rate is different from 12 MHz, we have to configure the\n+\t * FREQ field of the SFR_UTMICKTRIM register to generate properly\n+\t * the utmi clock.\n+\t */\n+\terr = clk_get_by_index(clk->dev, 0, &clk_dev);\n+\tif (err)\n+\t\treturn -EINVAL;\n+\n+\tclk_rate = clk_get_rate(&clk_dev);\n+\tswitch (clk_rate) {\n+\tcase 12000000:\n+\t\tutmi_ref_clk_freq = 0;\n+\t\tbreak;\n+\tcase 16000000:\n+\t\tutmi_ref_clk_freq = 1;\n+\t\tbreak;\n+\tcase 24000000:\n+\t\tutmi_ref_clk_freq = 2;\n+\t\tbreak;\n+\t/*\n+\t * Not supported on SAMA5D2 but it's not an issue since MAINCK\n+\t * maximum value is 24 MHz.\n+\t */\n+\tcase 48000000:\n+\t\tutmi_ref_clk_freq = 3;\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"UTMICK: unsupported mainck rate\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (plat->regmap_sfr) {\n+\t\terr = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);\n+\t\tif (err)\n+\t\t\treturn -EINVAL;\n+\n+\t\ttmp &= ~AT91_UTMICKTRIM_FREQ;\n+\t\ttmp |= utmi_ref_clk_freq;\n+\t\terr = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);\n+\t\tif (err)\n+\t\t\treturn -EINVAL;\n+\t} else if (utmi_ref_clk_freq) {\n+\t\tprintf(\"UTMICK: sfr node required\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \ttmp = readl(&pmc->uckr);\n \ttmp |= AT91_PMC_UPLLEN |\n \t AT91_PMC_UPLLCOUNT |\n@@ -39,7 +96,8 @@ static int utmi_clk_enable(struct clk *clk)\n \n static ulong utmi_clk_get_rate(struct clk *clk)\n {\n-\treturn gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL;\n+\t/* UTMI clk rate is fixed. */\n+\treturn UTMI_RATE;\n }\n \n static struct clk_ops utmi_clk_ops = {\n@@ -47,6 +105,20 @@ static struct clk_ops utmi_clk_ops = {\n \t.get_rate = utmi_clk_get_rate,\n };\n \n+static int utmi_clk_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct pmc_platdata *plat = dev_get_platdata(dev);\n+\tstruct udevice *syscon;\n+\n+\tuclass_get_device_by_phandle(UCLASS_SYSCON, dev,\n+\t\t\t\t \"regmap-sfr\", &syscon);\n+\n+\tif (syscon)\n+\t\tplat->regmap_sfr = syscon_get_regmap(syscon);\n+\n+\treturn 0;\n+}\n+\n static int utmi_clk_probe(struct udevice *dev)\n {\n \treturn at91_pmc_core_probe(dev);\n@@ -62,6 +134,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {\n \t.id = UCLASS_CLK,\n \t.of_match = utmi_clk_match,\n \t.probe = utmi_clk_probe,\n+\t.ofdata_to_platdata = utmi_clk_ofdata_to_platdata,\n \t.platdata_auto_alloc_size = sizeof(struct pmc_platdata),\n \t.ops = &utmi_clk_ops,\n };\ndiff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h\nindex bd3caba48d..5abda764a2 100644\n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -8,8 +8,11 @@\n #ifndef __AT91_PMC_H__\n #define __AT91_PMC_H__\n \n+#include <regmap.h>\n+\n struct pmc_platdata {\n \tstruct at91_pmc *reg_base;\n+\tstruct regmap *regmap_sfr;\n };\n \n int at91_pmc_core_probe(struct udevice *dev);\n", "prefixes": [ "U-Boot", "1/2" ] }