[{"id":1766651,"web_url":"http://patchwork.ozlabs.org/comment/1766651/","msgid":"<20170912024348.GA15157@bill-the-cat>","list_archive_url":null,"date":"2017-09-12T02:43:48","subject":"Re: [U-Boot] [U-Boot,\n\t1/2] clk: at91: utmi: Set the reference clock frequency","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Tue, Sep 05, 2017 at 06:30:07PM +0800, Wenyou Yang wrote:\n> By default, it is assumed that the UTMI clock is generated from\n> a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ\n> field of the SFR_UTMICKTRIM has to be updated to generate the UTMI\n> clock in the proper way.\n> \n> The UTMI clock has a fixed rate of 480 MHz. In fact, there is no\n> multiplier we can configure. The multiplier is managed internally,\n> depending on the reference clock frequency, to achieve the target\n> of 480 MHz.\n> \n> The patch is cloned from the patch of mailing-list:\n> \t[PATCH v2] clk: at91: utmi: set the mainck rate\n> \n> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>\n> ---\n> \n>  arch/arm/mach-at91/include/mach/sama5_sfr.h |  5 ++\n>  drivers/clk/at91/Kconfig                    |  4 ++\n>  drivers/clk/at91/clk-utmi.c                 | 77 ++++++++++++++++++++++++++++-\n>  drivers/clk/at91/pmc.h                      |  3 ++\n>  4 files changed, 87 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h\n> index b805a2c934..965631aad7 100644\n> --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h\n> +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h\n> @@ -28,6 +28,9 @@ struct atmel_sfr {\n>  \tu32 l2cc_hramc;\t/* 0x58 */\n>  };\n>  \n> +/* Register Mapping*/\n> +#define AT91_SFR_UTMICKTRIM\t0x30\t/* UTMI Clock Trimming Register */\n> +\n>  /* Bit field in DDRCFG */\n>  #define ATMEL_SFR_DDRCFG_FDQIEN\t\t0x00010000\n>  #define ATMEL_SFR_DDRCFG_FDQSIEN\t0x00020000\n> @@ -56,6 +59,8 @@ struct atmel_sfr {\n>  #define AT91_SFR_EBICFG_SCH1_OFF\t\t(0x0 << 12)\n>  #define AT91_SFR_EBICFG_SCH1_ON\t\t\t(0x1 << 12)\n>  \n> +#define AT91_UTMICKTRIM_FREQ\t\tGENMASK(1, 0)\n> +\n>  /* Bit field in AICREDIR */\n>  #define ATMEL_SFR_AICREDIR_NSAIC\t0x00000001\n>  \n> diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig\n> index 904ed48e51..2f112afa31 100644\n> --- a/drivers/clk/at91/Kconfig\n> +++ b/drivers/clk/at91/Kconfig\n> @@ -15,6 +15,10 @@ config CLK_AT91\n>  config AT91_UTMI\n>  \tbool \"Support UTMI PLL Clock\"\n>  \tdepends on CLK_AT91\n> +\tselect REGMAP\n> +\tselect SPL_REGMAP\n> +\tselect SYSCON\n> +\tselect SPL_SYSCON\n>  \thelp\n\nDoes this depend on other series in particular?  Not all boards that set\nAT91_UTMI also have SPL_DM enabled, which is required for SPL_REGMAP,\nthanks!","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=konsulko.com header.i=@konsulko.com\n\theader.b=\"dAA1nTSe\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrpy41GR0z9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 12:43:22 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 9C511C21F65; Tue, 12 Sep 2017 02:43:16 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9D30CC21DED;\n\tTue, 12 Sep 2017 02:43:14 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D762FC21DED; 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If it's not the case, the FREQ\n> field of the SFR_UTMICKTRIM has to be updated to generate the UTMI\n> clock in the proper way.\n> \n> The UTMI clock has a fixed rate of 480 MHz. In fact, there is no\n> multiplier we can configure. The multiplier is managed internally,\n> depending on the reference clock frequency, to achieve the target\n> of 480 MHz.\n> \n> The patch is cloned from the patch of mailing-list:\n> \t[PATCH v2] clk: at91: utmi: set the mainck rate\n> \n> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>\n\nApplied to u-boot/master, thanks!","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=konsulko.com header.i=@konsulko.com\n\theader.b=\"Lu2aFr6d\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtcFx396rz9sPr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 15 Sep 2017 10:48:21 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 2E03BC21F18; Fri, 15 Sep 2017 00:48:09 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 30629C21E52;\n\tFri, 15 Sep 2017 00:47:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 87400C21EF3; Fri, 15 Sep 2017 00:47:40 +0000 (UTC)","from mail-yw0-f170.google.com (mail-yw0-f170.google.com\n\t[209.85.161.170])\n\tby lists.denx.de (Postfix) with ESMTPS id 90497C21E79\n\tfor <u-boot@lists.denx.de>; Fri, 15 Sep 2017 00:47:36 +0000 (UTC)","by mail-yw0-f170.google.com with SMTP id v137so600155ywg.5\n\tfor <u-boot@lists.denx.de>; Thu, 14 Sep 2017 17:47:36 -0700 (PDT)","from bill-the-cat ([2606:a000:140b:dc:6c83:3e5c:b483:9b27])\n\tby smtp.gmail.com with ESMTPSA id\n\t205sm6048754ywz.68.2017.09.14.17.47.34\n\t(version=TLS1_2 cipher=AES128-SHA bits=128/128);\n\tThu, 14 Sep 2017 17:47:34 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=konsulko.com;\n\ts=google; \n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=731DhY7G/2qCpAMcCQ0ViDum6wbRZiwB4cZ1bn8epXQ=;\n\tb=Lu2aFr6dlpKClhMxPKE5XNC04bkyA/vD6S6z1w0l/DiGVuLPnL6RGE3puXmqpVoD0/\n\tbl9ykHReCyvmRl3lTgJueAT7xnyDcaQFtD6gXO9NFNYDLHSh+0gjxA9+zQir9KRJInOK\n\tLNlKBF12rtQSFtB9+iIin8eOcqqJfGZQ/ESO4=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=731DhY7G/2qCpAMcCQ0ViDum6wbRZiwB4cZ1bn8epXQ=;\n\tb=foam7bIJsRTSbcjMaN76BUXDkaCAVeLgWuHOk4Lp0NdTMmekXlQjmfoHJ595Y3ocXq\n\t5Yed2sdmOZsRzSH9Vl9CqRiJWG85gyJ6GEmhfIh0cfpbzK46UyT/PnzLTL3nzem7KA3k\n\tXbMn1OVsWws2IMGXMWpNaekfEKFrCG0N/RehytWw3CuqPwAP9v5aPowBQqpCv6ml5hXk\n\tJD1dvFaAsYZPGcxyvXMMBMvzNTvv2KHbXcIkqxSHsmBdfrDSLpJI+DyjflxZMVgJI7I0\n\ti5mirkSII3WKGj2XcNtYKf4Vk0Gf3L617G5Vcaeiz40HjxZDCOyrRNIqf0BhXCK/ah4r\n\tmteA==","X-Gm-Message-State":"AHPjjUgTU3mv74YPS7Wu9dh2BzJRoogX5c9YGkZmUwS5gFKJK5heIQTn\n\tYvzGSgnS69vhWmH9GQdu0A==","X-Google-Smtp-Source":"ADKCNb7ucpe/xXqphOgx87HHrHWIQbFSExFWSbwWQZsN2RgEO+X148Hl82GLzT2tm9o1VAn4UE58kQ==","X-Received":"by 10.37.6.69 with SMTP id 66mr11283580ybg.19.1505436455461;\n\tThu, 14 Sep 2017 17:47:35 -0700 (PDT)","Date":"Thu, 14 Sep 2017 20:47:32 -0400","From":"Tom Rini <trini@konsulko.com>","To":"Wenyou Yang <wenyou.yang@microchip.com>","Message-ID":"<20170915004732.GB4560@bill-the-cat>","References":"<20170905103008.3099-2-wenyou.yang@microchip.com>","MIME-Version":"1.0","In-Reply-To":"<20170905103008.3099-2-wenyou.yang@microchip.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Cc":"U-Boot Mailing List <u-boot@lists.denx.de>,\n\tStephen Warren <swarren@nvidia.com>","Subject":"Re: [U-Boot] [U-Boot,\n\t1/2] clk: at91: utmi: Set the reference clock frequency","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion <u-boot.lists.denx.de>","List-Unsubscribe":"<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>","List-Archive":"<http://lists.denx.de/pipermail/u-boot/>","List-Post":"<mailto:u-boot@lists.denx.de>","List-Help":"<mailto:u-boot-request@lists.denx.de?subject=help>","List-Subscribe":"<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>","Content-Type":"multipart/mixed;\n\tboundary=\"===============5734026812196630047==\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" <u-boot-bounces@lists.denx.de>"}}]