Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/809969/?format=api
{ "id": 809969, "url": "http://patchwork.ozlabs.org/api/patches/809969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504595552-9209-2-git-send-email-hean.loong.ong@intel.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504595552-9209-2-git-send-email-hean.loong.ong@intel.com>", "list_archive_url": null, "date": "2017-09-05T07:12:30", "name": "[PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "e9728168ff2be34d5a27e67ddff8e5a12187987d", "submitter": { "id": 70399, "url": "http://patchwork.ozlabs.org/api/people/70399/?format=api", "name": "Hean-Loong, Ong", "email": "hean.loong.ong@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504595552-9209-2-git-send-email-hean.loong.ong@intel.com/mbox/", "series": [ { "id": 1498, "url": "http://patchwork.ozlabs.org/api/series/1498/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=1498", "date": "2017-09-05T07:12:30", "name": "Intel FPGA Video and Image Processing Suite", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1498/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809969/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809969/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmdPx6qGWz9sP3\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 17:19:33 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751868AbdIEHTF (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 5 Sep 2017 03:19:05 -0400", "from mga04.intel.com ([192.55.52.120]:63357 \"EHLO mga04.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751623AbdIEHMk (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tTue, 5 Sep 2017 03:12:40 -0400", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t05 Sep 2017 00:12:40 -0700", "from helong-vb.png.intel.com ([10.226.242.102])\n\tby fmsmga002.fm.intel.com with ESMTP; 05 Sep 2017 00:12:37 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.41,479,1498546800\"; d=\"scan'208\";\n\ta=\"1214795486\"", "From": "\"Hean-Loong, Ong\" <hean.loong.ong@intel.com>", "To": "Rob Herring <robh+dt@kernel.org>, Dinh Nguyen <dinguyen@kernel.org>,\n\tDaniel Vetter <daniel.vetter@intel.com>,\n\tLaurent Pinchart <laurent.pinchart@ideasonboard.com>,\n\tRandy Dunlap <rdunlap@infradead.org>", "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdri-devel@lists.freedesktop.org, hean.loong.ong@intel.com,\n\tOng@vger.kernel.org", "Subject": "[PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image\n\tProcessing Suite", "Date": "Tue, 5 Sep 2017 15:12:30 +0800", "Message-Id": "<1504595552-9209-2-git-send-email-hean.loong.ong@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504595552-9209-1-git-send-email-hean.loong.ong@intel.com>", "References": "<1504595552-9209-1-git-send-email-hean.loong.ong@intel.com>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: Ong Hean Loong <hean.loong.ong@intel.com>\n\nDevice tree binding for Intel FPGA Video and Image\nProcessing Suite. The binding involved would be generated\nfrom the Altera (Intel) Qsys system. The bindings would\nset the max width, max height and memory port width.\nThe device tree binding only supports the Intel Arria10\ndevkit and its variants. Vendor name retained as altr.\n\nSigned-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>\n---\n\nV7:\n*Fix OF graph for better description\n*Add description for encoder\n\nV6:\n*Description have not describe DT device in general\n\nV5:\n*remove bindings for bits per symbol as it has only one value which is 8\n\nV4:\n*fix properties that does not describe the values\n\nV3:\n*OF graph not in accordance to graph.txt\n\nV2:\n*Remove Linux driver description\n\nV1:\n*Missing vendor prefix\n\n---\n---\n .../devicetree/bindings/display/altr,vip-fb2.txt | 74 ++++++++++++++++++++++\n 1 file changed, 74 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt", "diff": "diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt\nnew file mode 100644\nindex 0000000..bf0055d\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt\n@@ -0,0 +1,74 @@\n+Intel Video and Image Processing(VIP) Frame Buffer II bindings\n+\n+Supported hardware: Intel FPGA SoC Arria10 and above with display port IP\n+\n+The Video Frame Buffer II in Video Image Processing (VIP) suite is an IP core\n+that interfaces between system memory and Avalon-ST video ports. The IP core\n+can be configured to support the memory reader (from memory to Avalon-ST)\n+and/or memory writer (from Avalon-ST to memory) interfaces.\n+\n+More information the FPGA video IP component can be acquired from\n+https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\\\n+/literature/ug/ug_vip.pdf\n+\n+DT-Bindings:\n+=============\n+Required properties:\n+----------------------------\n+- compatible: \"altr,vip-frame-buffer-2.0\"\n+- reg: Physical base address and length of the framebuffer controller's\n+\tregisters.\n+- altr,max-width: The maximum width of the framebuffer in pixels.\n+- altr,max-height: The maximum height of the framebuffer in pixels.\n+- altr,mem-port-width = the bus width of the avalon master port\n+\ton the frame reader\n+\n+Connections between the Frame Buffer II and other video IP cores in the system\n+are modelled using the OF graph DT bindings. The Frame Buffer II node has up\n+to two OF graph ports. When the memory writer interface is enabled, port 0\n+maps to the Avalon-ST Input (din) port. When the memory reader interface is\n+enabled, port 1 maps to the Avalon-ST Output (dout) port.\n+\n+The encoder is built into the FPGA HW design and therefore would not\n+be accessible from the DDR.\n+\n+\t\tPort 0\t\t\t\tPort1\n+---------------------------------------------------------\n+ARRIA10 AVALON_ST (DIN)\t\tAVALON_ST (DOUT)\n+\n+Example:\n+----------------------------\n+\n+ +------------------------------+\n+ | FPGA | +------------+\n+ +---------+ +--------------+ | | DP |\n++-----+ | VIP | | DP | +----> Connector |\n+| | | Frame | | Controller | | | |\n+| D +----> Buffer | +--------------+ | +------------+\n+| D | | | +--------------+ |\n+| R | | | | DP | |\n+| | +---------+ | Encoder | |\n+| | | +--------------+ |\n++-----+ +------------------------------+\n+\n+\n+framebuffer@100000280 {\n+ compatible = \"altr,vip-frame-buffer-2.0\";\n+ reg = <0x00000001 0x00000280 0x00000040>;\n+ altr,max-width = <1280>;\n+ altr,max-height = <720>;\n+ altr,mem-port-width = <128>;\n+\n+ ports {\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+\n+ port@1 {\n+ reg = <1>;\n+ fb_output: endpoint {\n+ remote-endpoint = <&dp_encoder_input>;\n+ };\n+ };\n+ };\n+};\n+\n", "prefixes": [ "PATCHv7" ] }
