[{"id":1767388,"web_url":"http://patchwork.ozlabs.org/comment/1767388/","msgid":"<20170912214824.i7oab6kroqllzidc@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-12T21:48:24","subject":"Re: [PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image\n\tProcessing Suite","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Tue, Sep 05, 2017 at 03:12:30PM +0800, Hean-Loong, Ong wrote:\n> From: Ong Hean Loong <hean.loong.ong@intel.com>\n> \n> Device tree binding for Intel FPGA Video and Image\n> Processing Suite. The binding involved would be generated\n> from the Altera (Intel) Qsys system. The bindings would\n> set the max width, max height and memory port width.\n> The device tree binding only supports the Intel Arria10\n> devkit and its variants. Vendor name retained as altr.\n> \n> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>\n> ---\n\nAcked-by: Rob Herring <robh@kernel.org> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsJML27vzz9t3J\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 07:48:30 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751308AbdILVs1 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 12 Sep 2017 17:48:27 -0400","from mail-oi0-f51.google.com ([209.85.218.51]:36390 \"EHLO\n\tmail-oi0-f51.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751153AbdILVs0 (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 12 Sep 2017 17:48:26 -0400","by mail-oi0-f51.google.com with SMTP id x190so35743876oix.3;\n\tTue, 12 Sep 2017 14:48:26 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tq83sm10978150oif.4.2017.09.12.14.48.24\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 14:48:25 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=XADwCrkshcHGmZB7WckDiewduBH/5fE038JsKCrVjPU=;\n\tb=rXdiyqMi742HF6YxbTDWTjZi45GcfdGxLupPwyrXDRd9WjhfOtRMacio+UaTiIVZtl\n\t7wSjx41pCMgWaUgeCttua5odjg+CrQFrKoGRgkdRJseULqwwtBLeF3t2j27w7r8GDWgI\n\t+U6MTdWKmbzKaVogpcBQ+Xh7aW1kweWnGbGPrK1/mvOqBO3M+00q8Zeuyzd5iTS/lU1O\n\tlxuH98uHQUbt+0b3KoA4G7rPovoSicb7h5BrCrFJGTh2Szxk2oSu6le0AetHdRM4rm50\n\tMzkuaikVxm8HRZbqescWy5o3lScOgYFH1tYoZJYMXs5TcNtTJ39BGQgSG31aI2pS++DZ\n\tbkBQ==","X-Gm-Message-State":"AHPjjUjGur1Ap3AFkYtNn3F2N8KmJlmjf5NG4v9ACRloAK21VndnfhON\n\twhvlVWconUm7WA==","X-Google-Smtp-Source":"AOwi7QDUPpO+aPSNPYLFUxTyocs28gqSbfbuCUqps6F7DScdB6cYhPauGmg2TbX7nwRDSyUQL2i4Ag==","X-Received":"by 10.202.73.65 with SMTP id w62mr17196827oia.159.1505252905825; \n\tTue, 12 Sep 2017 14:48:25 -0700 (PDT)","Date":"Tue, 12 Sep 2017 16:48:24 -0500","From":"Rob Herring <robh@kernel.org>","To":"\"Hean-Loong, Ong\" <hean.loong.ong@intel.com>","Cc":"Dinh Nguyen <dinguyen@kernel.org>,\n\tDaniel Vetter <daniel.vetter@intel.com>, \n\tLaurent Pinchart <laurent.pinchart@ideasonboard.com>,\n\tRandy Dunlap <rdunlap@infradead.org>,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdri-devel@lists.freedesktop.org, Ong@rob-hp-laptop","Subject":"Re: [PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image\n\tProcessing Suite","Message-ID":"<20170912214824.i7oab6kroqllzidc@rob-hp-laptop>","References":"<1504595552-9209-1-git-send-email-hean.loong.ong@intel.com>\n\t<1504595552-9209-2-git-send-email-hean.loong.ong@intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504595552-9209-2-git-send-email-hean.loong.ong@intel.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}}]