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{ "id": 809610, "url": "http://patchwork.ozlabs.org/api/patches/809610/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/87d176itmx.fsf@linaro.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<87d176itmx.fsf@linaro.org>", "list_archive_url": null, "date": "2017-09-04T11:35:18", "name": "[4/9] Make mode_for_size return an opt_mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c91aabcd4b08d975a8e6104849d3937f12a1651a", "submitter": { "id": 5450, "url": "http://patchwork.ozlabs.org/api/people/5450/?format=api", "name": "Richard Sandiford", "email": "richard.sandiford@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/87d176itmx.fsf@linaro.org/mbox/", "series": [ { "id": 1357, "url": "http://patchwork.ozlabs.org/api/series/1357/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1357", "date": "2017-09-04T11:24:26", "name": "Make more use of opt_mode", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1357/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809610/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809610/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461406-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461406-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"I/BlUp/6\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm77t6Mxcz9s8J\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 21:35:38 +1000 (AEST)", "(qmail 93295 invoked by alias); 4 Sep 2017 11:35:30 -0000", "(qmail 93280 invoked by uid 89); 4 Sep 2017 11:35:30 -0000", "from mail-wr0-f179.google.com (HELO mail-wr0-f179.google.com)\n\t(209.85.128.179) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 04 Sep 2017 11:35:23 +0000", "by mail-wr0-f179.google.com with SMTP id 108so726953wra.5 for\n\t<gcc-patches@gcc.gnu.org>; Mon, 04 Sep 2017 04:35:23 -0700 (PDT)", "from localhost (94.197.120.41.threembb.co.uk. [94.197.120.41]) by\n\tsmtp.gmail.com with ESMTPSA id\n\t60sm1958191wrb.1.2017.09.04.04.35.19 for\n\t<gcc-patches@gcc.gnu.org> (version=TLS1_2\n\tcipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 04 Sep 2017 04:35:20 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:references:date:in-reply-to:message-id:mime-version\n\t:content-type; q=dns; s=default; b=pVHDBTPORe+sYaoE90zJSxYAVNGmw\n\tEx9a8WGtVFEhp77LAMPPaAM79G/iRPxDfWVUDEcLmocjwH6239YPvaqHK9LFjTPC\n\twFRVD5phGhj4NhetCH7jMnY3omftm/SM9/lfnSq9ra60MxtuN27wn7It/14y+ffR\n\tqLojC374NKpRG4=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:references:date:in-reply-to:message-id:mime-version\n\t:content-type; s=default; bh=bNjUw8kU0qErBHyGiBr2elpu4oU=; b=I/B\n\tlUp/6EQ3rfGO//Tpm+QoETL/jPEYQfcU7deTzyUTc16goUfsTutMJ4LAD4u9vWqU\n\tPwg/eeus+pVKzT20TllSpmsfDGD2bFpM7/b0w1n2JlQldfTl6OhZB02OxjQDISVu\n\tvwmHEb2q2xTdGsAei+KjPT/86Ssl6WNHWGS4FSbc=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-11.0 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=cope", "X-HELO": "mail-wr0-f179.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:mail-followup-to:subject:references:date\n\t:in-reply-to:message-id:user-agent:mime-version;\n\tbh=+wVLK3OVXUtMg50gn6CiQ4Oi6Q8EZpx8oNYOl7bKuds=;\n\tb=OAGjULP4a5XQcukzTSqhXNm490BrZUw3V3W1xqyBAMJD2mFTI46Wyg6/0xXLWz4GIo\n\tiz3NVwqSeHVVQqJEiDS7dKLY7PbTjt/Pgy8ATONEftc+WSyqfkU8wvjae8FA/6YdzG6p\n\tgoTeLU9SaLJmPgB4sMB92Y0i8glCV+t4hXrsdiaWnRIA1Ro5vFbtuUU4pcqbqxzLqpQg\n\tjO7/CeoJkodMlDLjJYWziLlbBR9rLyYWfX3EXTJTQLGc20LVH1d1aOwj3jQ5mREpQk4D\n\txpyUI6ikF1iDnnABRAtfjVdxLDPe7bBzniFSnzvrK40sgdYgq+nHOmfqEu0bHje9uOyH\n\ts5BQ==", "X-Gm-Message-State": "AHPjjUhzaQwLV9bGPszjpjywk2EQj671ayNNqKBh6vYt9rs/upPVGt0X\tIsYvTm3T0PkvWeEGZW2sbA==", "X-Google-Smtp-Source": "ADKCNb4oKtgilp6DuLJ3mX271D/S7xB82H+cEWU2XzEXd/+tiOfIeKeDgJDrcOP3T8cZUN/1YFoIzQ==", "X-Received": "by 10.223.155.157 with SMTP id d29mr151457wrc.24.1504524920915;\n\tMon, 04 Sep 2017 04:35:20 -0700 (PDT)", "From": "Richard Sandiford <richard.sandiford@linaro.org>", "To": "gcc-patches@gcc.gnu.org", "Mail-Followup-To": "gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org", "Subject": "[4/9] Make mode_for_size return an opt_mode", "References": "<87tw0iiu51.fsf@linaro.org>", "Date": "Mon, 04 Sep 2017 12:35:18 +0100", "In-Reply-To": "<87tw0iiu51.fsf@linaro.org> (Richard Sandiford's message of\n\t\"Mon, 04 Sep 2017 12:24:26 +0100\")", "Message-ID": "<87d176itmx.fsf@linaro.org>", "User-Agent": "Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux)", "MIME-Version": "1.0", "Content-Type": "text/plain" }, "content": "...to make it consistent with int_mode_for_size etc.\n\nrequire () seems like the right choice in replace_reg_with_saved_mem\nbecause we use the chosen mode for saving and restoring registers,\nwhich cannot be done in BLKmode. Similarly require () seems like\nthe right choice in calls related to secondary memory reloads (the ones\nin config/, and in get_secondary_mem) because the reload must always\nhave a defined mode, which e.g. determines the size of the slot.\n\nWe can use require () in simplify_subreg_concatn and assemble_integer\nbecause it isn't meaningful to create a subreg with BLKmode (for one\nthing, we couldn't tell then whether it was partial, paradoxical, etc.).\n\nmake_fract_type and make_accum_type must find a mode because that's\nwhat distinguishes accumulator FIXED_POINT_TYPEs from fractional\nFIXED_POINT_TYPEs.\n\n2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>\n\ngcc/\n\t* machmode.h (opt_machine_mode): New type.\n\t(opt_mode<T>): Allow construction from anything that can be\n\tconverted to a T.\n\t(is_a, as_a, dyn_cast): Add overloads for opt_mode.\n\t(mode_for_size): Return an opt_machine_mode.\n\t* stor-layout.c (mode_for_size): Likewise.\n\t(mode_for_size_tree): Update call accordingly.\n\t(bitwise_mode_for_mode): Likewise.\n\t(make_fract_type): Likewise.\n\t(make_accum_type): Likewise.\n\t* caller-save.c (replace_reg_with_saved_mem): Update call\n\taccordingly.\n\t* config/alpha/alpha.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n\t* config/i386/i386.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n\t* config/s390/s390.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n\t* config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n\t* expmed.c (extract_bit_field_1): Likewise.\n\t* reload.c (get_secondary_mem): Likewise.\n\t* varasm.c (assemble_integer): Likewise.\n\t* lower-subreg.c (simplify_subreg_concatn): Likewise. Move\n\tearly-out.", "diff": "Index: gcc/machmode.h\n===================================================================\n--- gcc/machmode.h\t2017-09-04 12:18:47.820398622 +0100\n+++ gcc/machmode.h\t2017-09-04 12:18:50.674859598 +0100\n@@ -20,6 +20,8 @@ Software Foundation; either version 3, o\n #ifndef HAVE_MACHINE_MODES\n #define HAVE_MACHINE_MODES\n \n+typedef opt_mode<machine_mode> opt_machine_mode;\n+\n extern CONST_MODE_SIZE unsigned short mode_size[NUM_MACHINE_MODES];\n extern const unsigned short mode_precision[NUM_MACHINE_MODES];\n extern const unsigned char mode_inner[NUM_MACHINE_MODES];\n@@ -237,6 +239,8 @@ #define POINTER_BOUNDS_MODE_P(MODE)\n \n ALWAYS_INLINE opt_mode () : m_mode (E_VOIDmode) {}\n ALWAYS_INLINE opt_mode (const T &m) : m_mode (m) {}\n+ template<typename U>\n+ ALWAYS_INLINE opt_mode (const U &m) : m_mode (T (m)) {}\n ALWAYS_INLINE opt_mode (from_int m) : m_mode (machine_mode (m)) {}\n \n machine_mode else_void () const;\n@@ -325,6 +329,13 @@ is_a (machine_mode m)\n return T::includes_p (m);\n }\n \n+template<typename T, typename U>\n+inline bool\n+is_a (const opt_mode<U> &m)\n+{\n+ return T::includes_p (m.else_void ());\n+}\n+\n /* Assert that mode M has type T, and return it in that form. */\n \n template<typename T>\n@@ -335,6 +346,13 @@ as_a (machine_mode m)\n return typename mode_traits<T>::from_int (m);\n }\n \n+template<typename T, typename U>\n+inline T\n+as_a (const opt_mode<U> &m)\n+{\n+ return as_a <T> (m.else_void ());\n+}\n+\n /* Convert M to an opt_mode<T>. */\n \n template<typename T>\n@@ -346,6 +364,13 @@ dyn_cast (machine_mode m)\n return opt_mode<T> ();\n }\n \n+template<typename T, typename U>\n+inline opt_mode<T>\n+dyn_cast (const opt_mode<U> &m)\n+{\n+ return dyn_cast <T> (m.else_void ());\n+}\n+\n /* Return true if mode M has type T, storing it as a T in *RESULT\n if so. */\n \n@@ -627,11 +652,7 @@ GET_MODE_2XWIDER_MODE (const T &m)\n extern const unsigned char mode_complex[NUM_MACHINE_MODES];\n #define GET_MODE_COMPLEX_MODE(MODE) ((machine_mode) mode_complex[MODE])\n \n-/* Return the mode for data of a given size SIZE and mode class CLASS.\n- If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE.\n- The value is BLKmode if no other mode is found. */\n-\n-extern machine_mode mode_for_size (unsigned int, enum mode_class, int);\n+extern opt_machine_mode mode_for_size (unsigned int, enum mode_class, int);\n \n /* Return the machine mode to use for a MODE_INT of SIZE bits, if one\n exists. If LIMIT is nonzero, modes wider than MAX_FIXED_MODE_SIZE\nIndex: gcc/stor-layout.c\n===================================================================\n--- gcc/stor-layout.c\t2017-09-04 12:18:44.944553324 +0100\n+++ gcc/stor-layout.c\t2017-09-04 12:18:50.675762071 +0100\n@@ -291,19 +291,19 @@ finalize_size_functions (void)\n vec_free (size_functions);\n }\n \f\n-/* Return the machine mode to use for a nonscalar of SIZE bits. The\n- mode must be in class MCLASS, and have exactly that many value bits;\n- it may have padding as well. If LIMIT is nonzero, modes of wider\n- than MAX_FIXED_MODE_SIZE will not be used. */\n+/* Return a machine mode of class MCLASS with SIZE bits of precision,\n+ if one exists. The mode may have padding bits as well the SIZE\n+ value bits. If LIMIT is nonzero, disregard modes wider than\n+ MAX_FIXED_MODE_SIZE. */\n \n-machine_mode\n+opt_machine_mode\n mode_for_size (unsigned int size, enum mode_class mclass, int limit)\n {\n machine_mode mode;\n int i;\n \n if (limit && size > MAX_FIXED_MODE_SIZE)\n- return BLKmode;\n+ return opt_machine_mode ();\n \n /* Get the first mode which has this size, in the specified class. */\n FOR_EACH_MODE_IN_CLASS (mode, mclass)\n@@ -316,7 +316,7 @@ mode_for_size (unsigned int size, enum m\n \t && int_n_enabled_p[i])\n \treturn int_n_data[i].m;\n \n- return BLKmode;\n+ return opt_machine_mode ();\n }\n \n /* Similar, except passed a tree node. */\n@@ -333,11 +333,11 @@ mode_for_size_tree (const_tree size, enu\n ui = uhwi;\n if (uhwi != ui)\n return BLKmode;\n- return mode_for_size (ui, mclass, limit);\n+ return mode_for_size (ui, mclass, limit).else_blk ();\n }\n \n-/* Similar, but never return BLKmode; return the narrowest mode that\n- contains at least the requested number of value bits. */\n+/* Return the narrowest mode of class MCLASS that contains at least\n+ SIZE bits. Abort if no such mode exists. */\n \n machine_mode\n smallest_mode_for_size (unsigned int size, enum mode_class mclass)\n@@ -426,9 +426,8 @@ bitwise_mode_for_mode (machine_mode mode\n if (COMPLEX_MODE_P (mode))\n {\n machine_mode trial = mode;\n- if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT)\n-\ttrial = mode_for_size (bitsize, MODE_COMPLEX_INT, false);\n- if (trial != BLKmode\n+ if ((GET_MODE_CLASS (trial) == MODE_COMPLEX_INT\n+\t || mode_for_size (bitsize, MODE_COMPLEX_INT, false).exists (&trial))\n \t && have_regs_of_mode[GET_MODE_INNER (trial)])\n \treturn trial;\n }\n@@ -438,16 +437,15 @@ bitwise_mode_for_mode (machine_mode mode\n if (VECTOR_MODE_P (mode) || bitsize > MAX_FIXED_MODE_SIZE)\n {\n machine_mode trial = mode;\n- if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)\n-\ttrial = mode_for_size (bitsize, MODE_VECTOR_INT, 0);\n- if (trial != BLKmode\n+ if ((GET_MODE_CLASS (trial) == MODE_VECTOR_INT\n+\t || mode_for_size (bitsize, MODE_VECTOR_INT, 0).exists (&trial))\n \t && have_regs_of_mode[trial]\n \t && targetm.vector_mode_supported_p (trial))\n \treturn trial;\n }\n \n /* Otherwise fall back on integers while honoring MAX_FIXED_MODE_SIZE. */\n- return mode_for_size (bitsize, MODE_INT, true);\n+ return mode_for_size (bitsize, MODE_INT, true).else_blk ();\n }\n \n /* Find a type that can be used for efficient bitwise operations on MODE.\n@@ -2543,13 +2541,9 @@ make_fract_type (int precision, int unsi\n TYPE_SATURATING (type) = 1;\n \n /* Lay out the type: set its alignment, size, etc. */\n- if (unsignedp)\n- {\n- TYPE_UNSIGNED (type) = 1;\n- SET_TYPE_MODE (type, mode_for_size (precision, MODE_UFRACT, 0));\n- }\n- else\n- SET_TYPE_MODE (type, mode_for_size (precision, MODE_FRACT, 0));\n+ TYPE_UNSIGNED (type) = unsignedp;\n+ enum mode_class mclass = unsignedp ? MODE_UFRACT : MODE_FRACT;\n+ SET_TYPE_MODE (type, mode_for_size (precision, mclass, 0).require ());\n layout_type (type);\n \n return type;\n@@ -2569,13 +2563,9 @@ make_accum_type (int precision, int unsi\n TYPE_SATURATING (type) = 1;\n \n /* Lay out the type: set its alignment, size, etc. */\n- if (unsignedp)\n- {\n- TYPE_UNSIGNED (type) = 1;\n- SET_TYPE_MODE (type, mode_for_size (precision, MODE_UACCUM, 0));\n- }\n- else\n- SET_TYPE_MODE (type, mode_for_size (precision, MODE_ACCUM, 0));\n+ TYPE_UNSIGNED (type) = unsignedp;\n+ enum mode_class mclass = unsignedp ? MODE_UACCUM : MODE_ACCUM;\n+ SET_TYPE_MODE (type, mode_for_size (precision, mclass, 0).require ());\n layout_type (type);\n \n return type;\nIndex: gcc/caller-save.c\n===================================================================\n--- gcc/caller-save.c\t2017-09-04 11:49:42.884500727 +0100\n+++ gcc/caller-save.c\t2017-09-04 12:18:50.672152181 +0100\n@@ -1161,7 +1161,7 @@ replace_reg_with_saved_mem (rtx *loc,\n \t gcc_assert (smode != VOIDmode);\n \t if (hard_regno_nregs [regno][smode] > 1)\n \t smode = mode_for_size (GET_MODE_SIZE (mode) / nregs,\n-\t\t\t\t GET_MODE_CLASS (mode), 0);\n+\t\t\t\t GET_MODE_CLASS (mode), 0).require ();\n \t XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i);\n \t }\n }\nIndex: gcc/config/alpha/alpha.h\n===================================================================\n--- gcc/config/alpha/alpha.h\t2017-09-04 11:50:08.504926375 +0100\n+++ gcc/config/alpha/alpha.h\t2017-09-04 12:18:50.672152181 +0100\n@@ -508,7 +508,7 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,C\n #define SECONDARY_MEMORY_NEEDED_MODE(MODE)\t\t\\\n (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE)\t\t\\\n : GET_MODE_SIZE (MODE) >= 4 ? (MODE)\t\t\t\\\n- : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))\n+ : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require ())\n \n /* Return the class of registers that cannot change mode from FROM to TO. */\n \nIndex: gcc/config/i386/i386.h\n===================================================================\n--- gcc/config/i386/i386.h\t2017-09-04 11:50:08.515731048 +0100\n+++ gcc/config/i386/i386.h\t2017-09-04 12:18:50.672152181 +0100\n@@ -1548,7 +1548,7 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n for integral modes that can be moved using 32 bit move. */\n #define SECONDARY_MEMORY_NEEDED_MODE(MODE)\t\t\t\\\n (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE)\t\\\n- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)\t\t\\\n+ ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require ()\t\\\n : MODE)\n \n /* Return a class of registers that cannot change FROM mode to TO mode. */\nIndex: gcc/config/s390/s390.h\n===================================================================\n--- gcc/config/s390/s390.h\t2017-09-04 11:50:24.561571751 +0100\n+++ gcc/config/s390/s390.h\t2017-09-04 12:18:50.673054653 +0100\n@@ -624,9 +624,9 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n \n /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit\n because the movsi and movsf patterns don't handle r/f moves. */\n-#define SECONDARY_MEMORY_NEEDED_MODE(MODE)\t\t\\\n- (GET_MODE_BITSIZE (MODE) < 32\t\t\t\t\\\n- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)\t\\\n+#define SECONDARY_MEMORY_NEEDED_MODE(MODE)\t\t\t\\\n+ (GET_MODE_BITSIZE (MODE) < 32\t\t\t\t\t\\\n+ ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require ()\t\\\n : (MODE))\n \n \nIndex: gcc/config/sparc/sparc.h\n===================================================================\n--- gcc/config/sparc/sparc.h\t2017-09-04 11:50:24.563372530 +0100\n+++ gcc/config/sparc/sparc.h\t2017-09-04 12:18:50.673054653 +0100\n@@ -1077,13 +1077,13 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9\n because the movsi and movsf patterns don't handle r/f moves.\n For v8 we copy the default definition. */\n-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n- (TARGET_ARCH64\t\t\t\t\t\t\\\n- ? (GET_MODE_BITSIZE (MODE) < 32\t\t\t\t\\\n- ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)\t\t\\\n- : MODE)\t\t\t\t\t\t\t\\\n- : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD\t\t\t\\\n- ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)\t\\\n+#define SECONDARY_MEMORY_NEEDED_MODE(MODE)\t\t\t\t \\\n+ (TARGET_ARCH64\t\t\t\t\t\t\t \\\n+ ? (GET_MODE_BITSIZE (MODE) < 32\t\t\t\t\t \\\n+ ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require ()\t\t \\\n+ : MODE)\t\t\t\t\t\t\t\t \\\n+ : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD\t\t\t\t \\\n+ ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require () \\\n : MODE))\n \n /* Return the maximum number of consecutive registers\nIndex: gcc/expmed.c\n===================================================================\n--- gcc/expmed.c\t2017-09-04 11:50:08.544543511 +0100\n+++ gcc/expmed.c\t2017-09-04 12:18:50.673054653 +0100\n@@ -1711,14 +1711,9 @@ extract_bit_field_1 (rtx str_rtx, unsign\n \n /* Get the mode of the field to use for atomic access or subreg\n conversion. */\n- mode1 = mode;\n- if (SCALAR_INT_MODE_P (tmode))\n- {\n- machine_mode try_mode = mode_for_size (bitsize,\n-\t\t\t\t\t\t GET_MODE_CLASS (tmode), 0);\n- if (try_mode != BLKmode)\n-\tmode1 = try_mode;\n- }\n+ if (!SCALAR_INT_MODE_P (tmode)\n+ || !mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0).exists (&mode1))\n+ mode1 = mode;\n gcc_assert (mode1 != BLKmode);\n \n /* Extraction of a full MODE1 value can be done with a subreg as long\nIndex: gcc/reload.c\n===================================================================\n--- gcc/reload.c\t2017-09-04 11:49:42.941500722 +0100\n+++ gcc/reload.c\t2017-09-04 12:18:50.675762071 +0100\n@@ -578,7 +578,8 @@ get_secondary_mem (rtx x ATTRIBUTE_UNUSE\n mode = SECONDARY_MEMORY_NEEDED_MODE (mode);\n #else\n if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode))\n- mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0);\n+ mode = mode_for_size (BITS_PER_WORD,\n+\t\t\t GET_MODE_CLASS (mode), 0).require ();\n #endif\n \n /* If we already have made a MEM for this operand in MODE, return it. */\nIndex: gcc/varasm.c\n===================================================================\n--- gcc/varasm.c\t2017-09-04 11:49:42.944500722 +0100\n+++ gcc/varasm.c\t2017-09-04 12:18:50.676664544 +0100\n@@ -2780,8 +2780,8 @@ assemble_integer (rtx x, unsigned int si\n else\n \tmclass = MODE_INT;\n \n- omode = mode_for_size (subsize * BITS_PER_UNIT, mclass, 0);\n- imode = mode_for_size (size * BITS_PER_UNIT, mclass, 0);\n+ omode = mode_for_size (subsize * BITS_PER_UNIT, mclass, 0).require ();\n+ imode = mode_for_size (size * BITS_PER_UNIT, mclass, 0).require ();\n \n for (i = 0; i < size; i += subsize)\n \t{\nIndex: gcc/lower-subreg.c\n===================================================================\n--- gcc/lower-subreg.c\t2017-09-04 12:18:41.572976650 +0100\n+++ gcc/lower-subreg.c\t2017-09-04 12:18:50.674859598 +0100\n@@ -616,20 +616,18 @@ simplify_subreg_concatn (machine_mode ou\n part = XVECEXP (op, 0, byte / inner_size);\n partmode = GET_MODE (part);\n \n+ final_offset = byte % inner_size;\n+ if (final_offset + GET_MODE_SIZE (outermode) > inner_size)\n+ return NULL_RTX;\n+\n /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of\n regular CONST_VECTORs. They have vector or integer modes, depending\n on the capabilities of the target. Cope with them. */\n if (partmode == VOIDmode && VECTOR_MODE_P (innermode))\n partmode = GET_MODE_INNER (innermode);\n else if (partmode == VOIDmode)\n- {\n- enum mode_class mclass = GET_MODE_CLASS (innermode);\n- partmode = mode_for_size (inner_size * BITS_PER_UNIT, mclass, 0);\n- }\n-\n- final_offset = byte % inner_size;\n- if (final_offset + GET_MODE_SIZE (outermode) > inner_size)\n- return NULL_RTX;\n+ partmode = mode_for_size (inner_size * BITS_PER_UNIT,\n+\t\t\t GET_MODE_CLASS (innermode), 0).require ();\n \n return simplify_gen_subreg (outermode, part, partmode, final_offset);\n }\n", "prefixes": [ "4/9" ] }