[{"id":1763245,"web_url":"http://patchwork.ozlabs.org/comment/1763245/","msgid":"","list_archive_url":null,"date":"2017-09-05T11:25:43","subject":"Re: [4/9] Make mode_for_size return an opt_mode","submitter":{"id":1765,"url":"http://patchwork.ozlabs.org/api/people/1765/","name":"Richard Biener","email":"richard.guenther@gmail.com"},"content":"On Mon, Sep 4, 2017 at 1:35 PM, Richard Sandiford\n wrote:\n> ...to make it consistent with int_mode_for_size etc.\n>\n> require () seems like the right choice in replace_reg_with_saved_mem\n> because we use the chosen mode for saving and restoring registers,\n> which cannot be done in BLKmode. Similarly require () seems like\n> the right choice in calls related to secondary memory reloads (the ones\n> in config/, and in get_secondary_mem) because the reload must always\n> have a defined mode, which e.g. determines the size of the slot.\n>\n> We can use require () in simplify_subreg_concatn and assemble_integer\n> because it isn't meaningful to create a subreg with BLKmode (for one\n> thing, we couldn't tell then whether it was partial, paradoxical, etc.).\n>\n> make_fract_type and make_accum_type must find a mode because that's\n> what distinguishes accumulator FIXED_POINT_TYPEs from fractional\n> FIXED_POINT_TYPEs.\n\nOk.\n\nRichard.\n\n> 2017-09-04 Richard Sandiford \n>\n> gcc/\n> * machmode.h (opt_machine_mode): New type.\n> (opt_mode): Allow construction from anything that can be\n> converted to a T.\n> (is_a, as_a, dyn_cast): Add overloads for opt_mode.\n> (mode_for_size): Return an opt_machine_mode.\n> * stor-layout.c (mode_for_size): Likewise.\n> (mode_for_size_tree): Update call accordingly.\n> (bitwise_mode_for_mode): Likewise.\n> (make_fract_type): Likewise.\n> (make_accum_type): Likewise.\n> * caller-save.c (replace_reg_with_saved_mem): Update call\n> accordingly.\n> * config/alpha/alpha.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n> * config/i386/i386.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n> * config/s390/s390.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n> * config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED_MODE): Likewise.\n> * expmed.c (extract_bit_field_1): Likewise.\n> * reload.c (get_secondary_mem): Likewise.\n> * varasm.c (assemble_integer): Likewise.\n> * lower-subreg.c (simplify_subreg_concatn): Likewise. Move\n> early-out.\n>\n> Index: gcc/machmode.h\n> ===================================================================\n> --- gcc/machmode.h 2017-09-04 12:18:47.820398622 +0100\n> +++ gcc/machmode.h 2017-09-04 12:18:50.674859598 +0100\n> @@ -20,6 +20,8 @@ Software Foundation; either version 3, o\n> #ifndef HAVE_MACHINE_MODES\n> #define HAVE_MACHINE_MODES\n>\n> +typedef opt_mode opt_machine_mode;\n> +\n> extern CONST_MODE_SIZE unsigned short mode_size[NUM_MACHINE_MODES];\n> extern const unsigned short mode_precision[NUM_MACHINE_MODES];\n> extern const unsigned char mode_inner[NUM_MACHINE_MODES];\n> @@ -237,6 +239,8 @@ #define POINTER_BOUNDS_MODE_P(MODE)\n>\n> ALWAYS_INLINE opt_mode () : m_mode (E_VOIDmode) {}\n> ALWAYS_INLINE opt_mode (const T &m) : m_mode (m) {}\n> + template\n> + ALWAYS_INLINE opt_mode (const U &m) : m_mode (T (m)) {}\n> ALWAYS_INLINE opt_mode (from_int m) : m_mode (machine_mode (m)) {}\n>\n> machine_mode else_void () const;\n> @@ -325,6 +329,13 @@ is_a (machine_mode m)\n> return T::includes_p (m);\n> }\n>\n> +template\n> +inline bool\n> +is_a (const opt_mode &m)\n> +{\n> + return T::includes_p (m.else_void ());\n> +}\n> +\n> /* Assert that mode M has type T, and return it in that form. */\n>\n> template\n> @@ -335,6 +346,13 @@ as_a (machine_mode m)\n> return typename mode_traits::from_int (m);\n> }\n>\n> +template\n> +inline T\n> +as_a (const opt_mode &m)\n> +{\n> + return as_a (m.else_void ());\n> +}\n> +\n> /* Convert M to an opt_mode. */\n>\n> template\n> @@ -346,6 +364,13 @@ dyn_cast (machine_mode m)\n> return opt_mode ();\n> }\n>\n> +template\n> +inline opt_mode\n> +dyn_cast (const opt_mode &m)\n> +{\n> + return dyn_cast (m.else_void ());\n> +}\n> +\n> /* Return true if mode M has type T, storing it as a T in *RESULT\n> if so. */\n>\n> @@ -627,11 +652,7 @@ GET_MODE_2XWIDER_MODE (const T &m)\n> extern const unsigned char mode_complex[NUM_MACHINE_MODES];\n> #define GET_MODE_COMPLEX_MODE(MODE) ((machine_mode) mode_complex[MODE])\n>\n> -/* Return the mode for data of a given size SIZE and mode class CLASS.\n> - If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE.\n> - The value is BLKmode if no other mode is found. */\n> -\n> -extern machine_mode mode_for_size (unsigned int, enum mode_class, int);\n> +extern opt_machine_mode mode_for_size (unsigned int, enum mode_class, int);\n>\n> /* Return the machine mode to use for a MODE_INT of SIZE bits, if one\n> exists. If LIMIT is nonzero, modes wider than MAX_FIXED_MODE_SIZE\n> Index: gcc/stor-layout.c\n> ===================================================================\n> --- gcc/stor-layout.c 2017-09-04 12:18:44.944553324 +0100\n> +++ gcc/stor-layout.c 2017-09-04 12:18:50.675762071 +0100\n> @@ -291,19 +291,19 @@ finalize_size_functions (void)\n> vec_free (size_functions);\n> }\n>\n> -/* Return the machine mode to use for a nonscalar of SIZE bits. The\n> - mode must be in class MCLASS, and have exactly that many value bits;\n> - it may have padding as well. If LIMIT is nonzero, modes of wider\n> - than MAX_FIXED_MODE_SIZE will not be used. */\n> +/* Return a machine mode of class MCLASS with SIZE bits of precision,\n> + if one exists. The mode may have padding bits as well the SIZE\n> + value bits. If LIMIT is nonzero, disregard modes wider than\n> + MAX_FIXED_MODE_SIZE. */\n>\n> -machine_mode\n> +opt_machine_mode\n> mode_for_size (unsigned int size, enum mode_class mclass, int limit)\n> {\n> machine_mode mode;\n> int i;\n>\n> if (limit && size > MAX_FIXED_MODE_SIZE)\n> - return BLKmode;\n> + return opt_machine_mode ();\n>\n> /* Get the first mode which has this size, in the specified class. */\n> FOR_EACH_MODE_IN_CLASS (mode, mclass)\n> @@ -316,7 +316,7 @@ mode_for_size (unsigned int size, enum m\n> && int_n_enabled_p[i])\n> return int_n_data[i].m;\n>\n> - return BLKmode;\n> + return opt_machine_mode ();\n> }\n>\n> /* Similar, except passed a tree node. */\n> @@ -333,11 +333,11 @@ mode_for_size_tree (const_tree size, enu\n> ui = uhwi;\n> if (uhwi != ui)\n> return BLKmode;\n> - return mode_for_size (ui, mclass, limit);\n> + return mode_for_size (ui, mclass, limit).else_blk ();\n> }\n>\n> -/* Similar, but never return BLKmode; return the narrowest mode that\n> - contains at least the requested number of value bits. */\n> +/* Return the narrowest mode of class MCLASS that contains at least\n> + SIZE bits. Abort if no such mode exists. */\n>\n> machine_mode\n> smallest_mode_for_size (unsigned int size, enum mode_class mclass)\n> @@ -426,9 +426,8 @@ bitwise_mode_for_mode (machine_mode mode\n> if (COMPLEX_MODE_P (mode))\n> {\n> machine_mode trial = mode;\n> - if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT)\n> - trial = mode_for_size (bitsize, MODE_COMPLEX_INT, false);\n> - if (trial != BLKmode\n> + if ((GET_MODE_CLASS (trial) == MODE_COMPLEX_INT\n> + || mode_for_size (bitsize, MODE_COMPLEX_INT, false).exists (&trial))\n> && have_regs_of_mode[GET_MODE_INNER (trial)])\n> return trial;\n> }\n> @@ -438,16 +437,15 @@ bitwise_mode_for_mode (machine_mode mode\n> if (VECTOR_MODE_P (mode) || bitsize > MAX_FIXED_MODE_SIZE)\n> {\n> machine_mode trial = mode;\n> - if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)\n> - trial = mode_for_size (bitsize, MODE_VECTOR_INT, 0);\n> - if (trial != BLKmode\n> + if ((GET_MODE_CLASS (trial) == MODE_VECTOR_INT\n> + || mode_for_size (bitsize, MODE_VECTOR_INT, 0).exists (&trial))\n> && have_regs_of_mode[trial]\n> && targetm.vector_mode_supported_p (trial))\n> return trial;\n> }\n>\n> /* Otherwise fall back on integers while honoring MAX_FIXED_MODE_SIZE. */\n> - return mode_for_size (bitsize, MODE_INT, true);\n> + return mode_for_size (bitsize, MODE_INT, true).else_blk ();\n> }\n>\n> /* Find a type that can be used for efficient bitwise operations on MODE.\n> @@ -2543,13 +2541,9 @@ make_fract_type (int precision, int unsi\n> TYPE_SATURATING (type) = 1;\n>\n> /* Lay out the type: set its alignment, size, etc. */\n> - if (unsignedp)\n> - {\n> - TYPE_UNSIGNED (type) = 1;\n> - SET_TYPE_MODE (type, mode_for_size (precision, MODE_UFRACT, 0));\n> - }\n> - else\n> - SET_TYPE_MODE (type, mode_for_size (precision, MODE_FRACT, 0));\n> + TYPE_UNSIGNED (type) = unsignedp;\n> + enum mode_class mclass = unsignedp ? MODE_UFRACT : MODE_FRACT;\n> + SET_TYPE_MODE (type, mode_for_size (precision, mclass, 0).require ());\n> layout_type (type);\n>\n> return type;\n> @@ -2569,13 +2563,9 @@ make_accum_type (int precision, int unsi\n> TYPE_SATURATING (type) = 1;\n>\n> /* Lay out the type: set its alignment, size, etc. */\n> - if (unsignedp)\n> - {\n> - TYPE_UNSIGNED (type) = 1;\n> - SET_TYPE_MODE (type, mode_for_size (precision, MODE_UACCUM, 0));\n> - }\n> - else\n> - SET_TYPE_MODE (type, mode_for_size (precision, MODE_ACCUM, 0));\n> + TYPE_UNSIGNED (type) = unsignedp;\n> + enum mode_class mclass = unsignedp ? MODE_UACCUM : MODE_ACCUM;\n> + SET_TYPE_MODE (type, mode_for_size (precision, mclass, 0).require ());\n> layout_type (type);\n>\n> return type;\n> Index: gcc/caller-save.c\n> ===================================================================\n> --- gcc/caller-save.c 2017-09-04 11:49:42.884500727 +0100\n> +++ gcc/caller-save.c 2017-09-04 12:18:50.672152181 +0100\n> @@ -1161,7 +1161,7 @@ replace_reg_with_saved_mem (rtx *loc,\n> gcc_assert (smode != VOIDmode);\n> if (hard_regno_nregs [regno][smode] > 1)\n> smode = mode_for_size (GET_MODE_SIZE (mode) / nregs,\n> - GET_MODE_CLASS (mode), 0);\n> + GET_MODE_CLASS (mode), 0).require ();\n> XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i);\n> }\n> }\n> Index: gcc/config/alpha/alpha.h\n> ===================================================================\n> --- gcc/config/alpha/alpha.h 2017-09-04 11:50:08.504926375 +0100\n> +++ gcc/config/alpha/alpha.h 2017-09-04 12:18:50.672152181 +0100\n> @@ -508,7 +508,7 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,C\n> #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \\\n> : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \\\n> - : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))\n> + : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require ())\n>\n> /* Return the class of registers that cannot change mode from FROM to TO. */\n>\n> Index: gcc/config/i386/i386.h\n> ===================================================================\n> --- gcc/config/i386/i386.h 2017-09-04 11:50:08.515731048 +0100\n> +++ gcc/config/i386/i386.h 2017-09-04 12:18:50.672152181 +0100\n> @@ -1548,7 +1548,7 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n> for integral modes that can be moved using 32 bit move. */\n> #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \\\n> - ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \\\n> + ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \\\n> : MODE)\n>\n> /* Return a class of registers that cannot change FROM mode to TO mode. */\n> Index: gcc/config/s390/s390.h\n> ===================================================================\n> --- gcc/config/s390/s390.h 2017-09-04 11:50:24.561571751 +0100\n> +++ gcc/config/s390/s390.h 2017-09-04 12:18:50.673054653 +0100\n> @@ -624,9 +624,9 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n>\n> /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit\n> because the movsi and movsf patterns don't handle r/f moves. */\n> -#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> - (GET_MODE_BITSIZE (MODE) < 32 \\\n> - ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \\\n> +#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> + (GET_MODE_BITSIZE (MODE) < 32 \\\n> + ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \\\n> : (MODE))\n>\n>\n> Index: gcc/config/sparc/sparc.h\n> ===================================================================\n> --- gcc/config/sparc/sparc.h 2017-09-04 11:50:24.563372530 +0100\n> +++ gcc/config/sparc/sparc.h 2017-09-04 12:18:50.673054653 +0100\n> @@ -1077,13 +1077,13 @@ #define SECONDARY_MEMORY_NEEDED(CLASS1,\n> /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9\n> because the movsi and movsf patterns don't handle r/f moves.\n> For v8 we copy the default definition. */\n> -#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> - (TARGET_ARCH64 \\\n> - ? (GET_MODE_BITSIZE (MODE) < 32 \\\n> - ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \\\n> - : MODE) \\\n> - : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \\\n> - ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \\\n> +#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \\\n> + (TARGET_ARCH64 \\\n> + ? (GET_MODE_BITSIZE (MODE) < 32 \\\n> + ? mode_for_size (32, GET_MODE_CLASS (MODE), 0).require () \\\n> + : MODE) \\\n> + : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \\\n> + ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0).require () \\\n> : MODE))\n>\n> /* Return the maximum number of consecutive registers\n> Index: gcc/expmed.c\n> ===================================================================\n> --- gcc/expmed.c 2017-09-04 11:50:08.544543511 +0100\n> +++ gcc/expmed.c 2017-09-04 12:18:50.673054653 +0100\n> @@ -1711,14 +1711,9 @@ extract_bit_field_1 (rtx str_rtx, unsign\n>\n> /* Get the mode of the field to use for atomic access or subreg\n> conversion. */\n> - mode1 = mode;\n> - if (SCALAR_INT_MODE_P (tmode))\n> - {\n> - machine_mode try_mode = mode_for_size (bitsize,\n> - GET_MODE_CLASS (tmode), 0);\n> - if (try_mode != BLKmode)\n> - mode1 = try_mode;\n> - }\n> + if (!SCALAR_INT_MODE_P (tmode)\n> + || !mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0).exists (&mode1))\n> + mode1 = mode;\n> gcc_assert (mode1 != BLKmode);\n>\n> /* Extraction of a full MODE1 value can be done with a subreg as long\n> Index: gcc/reload.c\n> ===================================================================\n> --- gcc/reload.c 2017-09-04 11:49:42.941500722 +0100\n> +++ gcc/reload.c 2017-09-04 12:18:50.675762071 +0100\n> @@ -578,7 +578,8 @@ get_secondary_mem (rtx x ATTRIBUTE_UNUSE\n> mode = SECONDARY_MEMORY_NEEDED_MODE (mode);\n> #else\n> if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode))\n> - mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0);\n> + mode = mode_for_size (BITS_PER_WORD,\n> + GET_MODE_CLASS (mode), 0).require ();\n> #endif\n>\n> /* If we already have made a MEM for this operand in MODE, return it. */\n> Index: gcc/varasm.c\n> ===================================================================\n> --- gcc/varasm.c 2017-09-04 11:49:42.944500722 +0100\n> +++ gcc/varasm.c 2017-09-04 12:18:50.676664544 +0100\n> @@ -2780,8 +2780,8 @@ assemble_integer (rtx x, unsigned int si\n> else\n> mclass = MODE_INT;\n>\n> - omode = mode_for_size (subsize * BITS_PER_UNIT, mclass, 0);\n> - imode = mode_for_size (size * BITS_PER_UNIT, mclass, 0);\n> + omode = mode_for_size (subsize * BITS_PER_UNIT, mclass, 0).require ();\n> + imode = mode_for_size (size * BITS_PER_UNIT, mclass, 0).require ();\n>\n> for (i = 0; i < size; i += subsize)\n> {\n> Index: gcc/lower-subreg.c\n> ===================================================================\n> --- gcc/lower-subreg.c 2017-09-04 12:18:41.572976650 +0100\n> +++ gcc/lower-subreg.c 2017-09-04 12:18:50.674859598 +0100\n> @@ -616,20 +616,18 @@ simplify_subreg_concatn (machine_mode ou\n> part = XVECEXP (op, 0, byte / inner_size);\n> partmode = GET_MODE (part);\n>\n> + final_offset = byte % inner_size;\n> + if (final_offset + GET_MODE_SIZE (outermode) > inner_size)\n> + return NULL_RTX;\n> +\n> /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of\n> regular CONST_VECTORs. They have vector or integer modes, depending\n> on the capabilities of the target. Cope with them. */\n> if (partmode == VOIDmode && VECTOR_MODE_P (innermode))\n> partmode = GET_MODE_INNER (innermode);\n> else if (partmode == VOIDmode)\n> - {\n> - enum mode_class mclass = GET_MODE_CLASS (innermode);\n> - partmode = mode_for_size (inner_size * BITS_PER_UNIT, mclass, 0);\n> - }\n> -\n> - final_offset = byte % inner_size;\n> - if (final_offset + GET_MODE_SIZE (outermode) > inner_size)\n> - return NULL_RTX;\n> + partmode = mode_for_size (inner_size * BITS_PER_UNIT,\n> + GET_MODE_CLASS (innermode), 0).require ();\n>\n> return simplify_gen_subreg (outermode, part, partmode, final_offset);\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461491-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"EzTTfOho\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmktQ0VFsz9s3T\n\tfor ;\n\tTue, 5 Sep 2017 21:26:05 +1000 (AEST)","(qmail 3543 invoked by alias); 5 Sep 2017 11:25:54 -0000","(qmail 3530 invoked by uid 89); 5 Sep 2017 11:25:53 -0000","from mail-wm0-f48.google.com (HELO mail-wm0-f48.google.com)\n\t(74.125.82.48) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 05 Sep 2017 11:25:47 +0000","by mail-wm0-f48.google.com with SMTP id i145so17830448wmf.1 for\n\t; Tue, 05 Sep 2017 04:25:46 -0700 (PDT)","by 10.80.180.205 with HTTP; Tue, 5 Sep 2017 04:25:43 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:content-type; q=dns; s=default; b=CIaOz6D/LGu35Ca/Ce\n\trKU2muufdMWKJr53PM6/ZMItlfaXu94HpKUaJaA6VHDq3bImlRWtgwlO4MzpeAgZ\n\tQOGTtqimT5pYqyoEYVkDvPAjRho/hEYQl1m0+40YLWYnwuksN0tL+iCT5Vm0aYw2\n\t3vSAsqF/k8jbAw4mJHOXHrHD8=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:content-type; s=default; bh=Nu+8VanX4xmfQ4S/PQTHGppb\n\tTbM=; b=EzTTfOho5+Jg/KO/2A9o2vhIYo5v/FIo79LiXv9N7gjMyO9YAPf1GzoP\n\tQ0CKCE0Y30Hseu2LlGaM4Q4qVcQOTL10W4hV4qn3+ofb4+/222/F3BUu/6cgozM6\n\tyrk2t+x0D+Nnb01bNNef0ublIB1ZjwCAhOQDYp1kjfQUhHfjwCM=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-10.2 required=5.0 tests=AWL, BAYES_00,\n\tFREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"mail-wm0-f48.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to;\n\tbh=H742Dti+OKi88qIFJ1+KBk0FnkhqwBREtmnjqJWEc+o=;\n\tb=l3VgvP6MFaPyLU9CsjES7C3bXUTccUKQUckc1VeGsCGOv5qMKuP/tw0ijnakaOtGAq\n\tcPHxPMNoWDY4Bm0xhNl0F3TNDHKtcIZIUqEjDlcOKHl8FHbo+cTTGsPVXQnmIV1J1C2J\n\tIRPLBc9cqzx81+zHQYe4OrNuGJ/Xt1tRUi5b/Hq1NUqhi1pblpFMlNCKq1tRLlcPe+H5\n\trli1pZbDbDJgnpiaW/R1grnoxGurIMX2XyXebMtNWEaTHCtJuRoJM+uC9PjBkuKDxDWo\n\tsHaw58cY0gW0g1Qhamt0cOUGJYFN9SyJAdCM/WpIWbMGV8OqmHMYL6+ZRgAbb3czfC/M\n\t+t+A==","X-Gm-Message-State":"AHPjjUge47We6pG8E2MUtCuVO7ZFk0hBirLGazXjmrUCNdm1170okTBo\tHiFXB3HA3afW+MYWFuMARmjV6Y1H0RZi","X-Google-Smtp-Source":"ADKCNb4Fp+spxiJviAOzBvtrjBFRiKIl8lLySIZrfL2rDoJgvK46tkl2/02gGZx98I5SJq7WlkcfJqOmma53aBFtMWo=","X-Received":"by 10.80.240.26 with SMTP id r26mr3052382edl.142.1504610744180;\n\tTue, 05 Sep 2017 04:25:44 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<87d176itmx.fsf@linaro.org>","References":"<87tw0iiu51.fsf@linaro.org> <87d176itmx.fsf@linaro.org>","From":"Richard Biener ","Date":"Tue, 5 Sep 2017 13:25:43 +0200","Message-ID":"","Subject":"Re: [4/9] Make mode_for_size return an opt_mode","To":"GCC Patches ,\n\tRichard Sandiford ","Content-Type":"text/plain; charset=\"UTF-8\"","X-IsSubscribed":"yes"}}]