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GET /api/patches/809532/?format=api
{ "id": 809532, "url": "http://patchwork.ozlabs.org/api/patches/809532/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504506242-31430-2-git-send-email-rajesh.bhagat@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504506242-31430-2-git-send-email-rajesh.bhagat@nxp.com>", "list_archive_url": null, "date": "2017-09-04T06:23:56", "name": "[U-Boot,RESEND,v3,1/7] armv8: lsch3: Add serdes and DDR voltage setup", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "9faa8b4f7515745ad3123fc1a64513bd9c5d9585", "submitter": { "id": 68498, "url": "http://patchwork.ozlabs.org/api/people/68498/?format=api", "name": "Rajesh Bhagat", "email": "rajesh.bhagat@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504506242-31430-2-git-send-email-rajesh.bhagat@nxp.com/mbox/", "series": [ { "id": 1314, "url": "http://patchwork.ozlabs.org/api/series/1314/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1314", "date": "2017-09-04T06:23:56", "name": "Add VID support for QDS and RDB platforms", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/1314/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809532/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809532/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Sun, 3 Sep 2017 23:24:09 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Rajesh Bhagat <rajesh.bhagat@nxp.com>", "To": "<u-boot@lists.denx.de>", "Date": "Mon, 4 Sep 2017 11:53:56 +0530", "Message-ID": "<1504506242-31430-2-git-send-email-rajesh.bhagat@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504506242-31430-1-git-send-email-rajesh.bhagat@nxp.com>", "References": "<1504506242-31430-1-git-send-email-rajesh.bhagat@nxp.com>", "MIME-Version": "1.0", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131489798519906583;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY4PR03MB3320; ", "X-Forefront-PRVS": "0420213CCD", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2017 06:24:11.8190\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR03MB3320", "Subject": "[U-Boot] [RESEND PATCH v3 1/7] armv8: lsch3: Add serdes and DDR\n\tvoltage setup", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Adds SERDES voltage and reset SERDES lanes API and makes\nenable/disable DDR controller support 0.9V API common.\n\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\n---\nChanges in v3:\n Restructured LS1088A VID support to use common VID driver\n Cosmetic review comments fixed\n Added __iomem for accessing registers\n\nChanges in v2:\n Checkpatch errors fixed\n\n .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 274 +++++++++++++++++++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 34 +--\n .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++\n arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +\n 5 files changed, 327 insertions(+), 18 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\nindex 179cac6..39f2cdf 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n@@ -158,6 +158,280 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,\n \tserdes_prtcl_map[NONE] = 1;\n }\n \n+__weak int get_serdes_volt(void)\n+{\n+\treturn -1;\n+}\n+\n+__weak int set_serdes_volt(int svdd)\n+{\n+\treturn -1;\n+}\n+\n+int setup_serdes_volt(u32 svdd)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tstruct ccsr_serdes __iomem *serdes1_base;\n+\tu32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tstruct ccsr_serdes __iomem *serdes2_base;\n+\tu32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);\n+#endif\n+\tu32 cfg_tmp, reg = 0;\n+\tint svdd_cur, svdd_tar;\n+\tint ret = 1;\n+\tint i;\n+\n+\t/* Only support switch SVDD to 900mV */\n+\tif (svdd != 900)\n+\t\treturn -1;\n+\n+\t/* Scale up to the LTC resolution is 1/4096V */\n+\tsvdd = (svdd * 4096) / 1000;\n+\n+\tsvdd_tar = svdd;\n+\tsvdd_cur = get_serdes_volt();\n+\tif (svdd_cur < 0)\n+\t\treturn -EINVAL;\n+\n+\tdebug(\"%s: current SVDD: %x; target SVDD: %x\\n\",\n+\t __func__, svdd_cur, svdd_tar);\n+\tif (svdd_cur == svdd_tar)\n+\t\treturn 0;\n+\n+\tserdes1_base = (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tserdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);\n+#endif\n+\n+\t/* Put the all enabled lanes in reset */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\n+\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n+\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n+\t\treg &= 0xFF9FFFFF;\n+\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n+\t}\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n+\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n+\n+\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n+\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n+\t\treg &= 0xFF9FFFFF;\n+\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n+\t}\n+#endif\n+\n+\t/* Put the all enabled PLL in reset */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\treg &= 0xFFFFFFBF;\n+\t\treg |= 0x10000000;\n+\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t}\n+\tudelay(1);\n+\n+\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\treg &= 0xFFFFFF1F;\n+\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n+\tcfg_tmp >>= 2;\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\treg &= 0xFFFFFFBF;\n+\t\treg |= 0x10000000;\n+\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t}\n+\tudelay(1);\n+\n+\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\treg &= 0xFFFFFF1F;\n+\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+#endif\n+\n+\t/* Put the Rx/Tx calibration into reset */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\treg = in_le32(&serdes1_base->srdstcalcr);\n+\treg &= 0xF7FFFFFF;\n+\tout_le32(&serdes1_base->srdstcalcr, reg);\n+\treg = in_le32(&serdes1_base->srdsrcalcr);\n+\treg &= 0xF7FFFFFF;\n+\tout_le32(&serdes1_base->srdsrcalcr, reg);\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\treg = in_le32(&serdes2_base->srdstcalcr);\n+\treg &= 0xF7FFFFFF;\n+\tout_le32(&serdes2_base->srdstcalcr, reg);\n+\treg = in_le32(&serdes2_base->srdsrcalcr);\n+\treg &= 0xF7FFFFFF;\n+\tout_le32(&serdes2_base->srdsrcalcr, reg);\n+#endif\n+\n+\tret = set_serdes_volt(svdd);\n+\tif (ret < 0) {\n+\t\tprintf(\"could not change SVDD\\n\");\n+\t\tret = -1;\n+\t}\n+\n+\t/* For each PLL that’s not disabled via RCW enable the SERDES */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\treg |= 0x00000020;\n+\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t\tudelay(1);\n+\n+\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\treg |= 0x00000080;\n+\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t\tudelay(1);\n+\t\t/* Take the Rx/Tx calibration out of reset */\n+\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n+\t\t\tudelay(1);\n+\t\t\treg = in_le32(&serdes1_base->srdstcalcr);\n+\t\t\treg |= 0x08000000;\n+\t\t\tout_le32(&serdes1_base->srdstcalcr, reg);\n+\t\t\treg = in_le32(&serdes1_base->srdsrcalcr);\n+\t\t\treg |= 0x08000000;\n+\t\t\tout_le32(&serdes1_base->srdsrcalcr, reg);\n+\t\t}\n+\t\tudelay(1);\n+\t}\n+#endif\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n+\tcfg_tmp >>= 2;\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\treg |= 0x00000020;\n+\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t\tudelay(1);\n+\n+\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\treg |= 0x00000080;\n+\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t\tudelay(1);\n+\n+\t\t/* Take the Rx/Tx calibration out of reset */\n+\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n+\t\t\tudelay(1);\n+\t\t\treg = in_le32(&serdes2_base->srdstcalcr);\n+\t\t\treg |= 0x08000000;\n+\t\t\tout_le32(&serdes2_base->srdstcalcr, reg);\n+\t\t\treg = in_le32(&serdes2_base->srdsrcalcr);\n+\t\t\treg |= 0x08000000;\n+\t\t\tout_le32(&serdes2_base->srdsrcalcr, reg);\n+\t\t}\n+\t\tudelay(1);\n+\t}\n+#endif\n+\n+\t/* Wait for at atleast 625us, ensure the PLLs being reset are locked */\n+\tudelay(800);\n+\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\t/* if the PLL is not locked, set RST_ERR */\n+\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n+\t\tif (!((reg >> 23) & 0x1)) {\n+\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\t\treg |= 0x20000000;\n+\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t\t} else {\n+\t\t\tudelay(1);\n+\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\t\treg &= 0xFFFFFFEF;\n+\t\t\treg |= 0x00000040;\n+\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t\t\tudelay(1);\n+\t\t}\n+\t}\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n+\tcfg_tmp >>= 2;\n+\n+\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n+\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n+\t\tif (!((reg >> 23) & 0x1)) {\n+\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\t\treg |= 0x20000000;\n+\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t\t} else {\n+\t\t\tudelay(1);\n+\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\t\treg &= 0xFFFFFFEF;\n+\t\t\treg |= 0x00000040;\n+\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t\t\tudelay(1);\n+\t\t}\n+\t}\n+#endif\n+\t/* Take the all enabled lanes out of reset */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\n+\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n+\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n+\t\treg |= 0x00600000;\n+\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n+\t}\n+#endif\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n+\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n+\n+\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n+\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n+\t\treg |= 0x00600000;\n+\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n+\t}\n+#endif\n+\n+\t/* For each PLL being reset, and achieved PLL lock set RST_DONE */\n+#ifdef CONFIG_SYS_FSL_SRDS_1\n+\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n+\tfor (i = 0; i < 2; i++) {\n+\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n+\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n+\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n+\t\t\treg |= 0x40000000;\n+\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n+\t\t}\n+\t}\n+#endif\n+#ifdef CONFIG_SYS_FSL_SRDS_2\n+\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n+\tcfg_tmp >>= 2;\n+\n+\tfor (i = 0; i < 2; i++) {\n+\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n+\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n+\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n+\t\t\treg |= 0x40000000;\n+\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n+\t\t}\n+\t}\n+#endif\n+\n+\treturn ret;\n+}\n+\n void fsl_serdes_init(void)\n {\n #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 83e2871..4e96c7b 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -404,23 +404,6 @@ static int setup_core_volt(u32 vdd)\n \treturn board_setup_core_volt(vdd);\n }\n \n-#ifdef CONFIG_SYS_FSL_DDR\n-static void ddr_enable_0v9_volt(bool en)\n-{\n-\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n-\tu32 tmp;\n-\n-\ttmp = ddr_in32(&ddr->ddr_cdr1);\n-\n-\tif (en)\n-\t\ttmp |= DDR_CDR1_V0PT9_EN;\n-\telse\n-\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n-\n-\tddr_out32(&ddr->ddr_cdr1, tmp);\n-}\n-#endif\n-\n int setup_chip_volt(void)\n {\n \tint vdd;\n@@ -485,6 +468,23 @@ void fsl_lsch2_early_init_f(void)\n }\n #endif\n \n+#ifdef CONFIG_SYS_FSL_DDR\n+void ddr_enable_0v9_volt(bool en)\n+{\n+\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n+\tu32 tmp;\n+\n+\ttmp = ddr_in32(&ddr->ddr_cdr1);\n+\n+\tif (en)\n+\t\ttmp |= DDR_CDR1_V0PT9_EN;\n+\telse\n+\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n+\n+\tddr_out32(&ddr->ddr_cdr1, tmp);\n+}\n+#endif\n+\n #ifdef CONFIG_QSPI_AHB_INIT\n /* Enable 4bytes address support and fast read */\n int qspi_ahb_init(void)\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\nindex 12fd6b8..9becdf3 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n@@ -164,6 +164,7 @@ void fsl_rgmii_init(void);\n #ifdef CONFIG_FSL_LSCH2\n const char *serdes_clock_to_string(u32 clock);\n int get_serdes_protocol(void);\n+#endif\n #ifdef CONFIG_SYS_HAS_SERDES\n /* Get the volt of SVDD in unit mV */\n int get_serdes_volt(void);\n@@ -172,6 +173,5 @@ int set_serdes_volt(int svdd);\n /* The target volt of SVDD in unit mV */\n int setup_serdes_volt(u32 svdd);\n #endif\n-#endif\n \n #endif /* __FSL_SERDES_H__ */\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex ffc5fa2..2706ea8 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -370,5 +370,39 @@ struct ccsr_reset {\n \tu32 ip_rev2;\t\t\t/* 0xbfc */\n };\n \n+struct ccsr_serdes {\n+\tstruct {\n+\t\tu32 rstctl; /* Reset Control Register */\n+\t\tu32 pllcr0; /* PLL Control Register 0 */\n+\t\tu32 pllcr1; /* PLL Control Register 1 */\n+\t\tu32 pllcr2; /* PLL Control Register 2 */\n+\t\tu32 pllcr3; /* PLL Control Register 3 */\n+\t\tu32 pllcr4; /* PLL Control Register 4 */\n+\t\tu32 pllcr5; /* PLL Control Register 5 */\n+\t\tu8 res[0x20 - 0x1c];\n+\t} bank[2];\n+\tu8 res1[0x90 - 0x40];\n+\tu32 srdstcalcr; /* TX Calibration Control */\n+\tu32 srdstcalcr1; /* TX Calibration Control1 */\n+\tu8 res2[0xa0 - 0x98];\n+\tu32 srdsrcalcr; /* RX Calibration Control */\n+\tu32 srdsrcalcr1; /* RX Calibration Control1 */\n+\tu8 res3[0xb0 - 0xa8];\n+\tu32 srdsgr0; /* General Register 0 */\n+\tu8 res4[0x800 - 0xb4];\n+\tstruct serdes_lane {\n+\t\tu32 gcr0; /* General Control Register 0 */\n+\t\tu32 gcr1; /* General Control Register 1 */\n+\t\tu32 gcr2; /* General Control Register 2 */\n+\t\tu32 ssc0; /* Speed Switch Control 0 */\n+\t\tu32 rec0; /* Receive Equalization Control 0 */\n+\t\tu32 rec1; /* Receive Equalization Control 1 */\n+\t\tu32 tec0; /* Transmit Equalization Control 0 */\n+\t\tu32 ssc1; /* Speed Switch Control 1 */\n+\t\tu8 res1[0x840 - 0x820];\n+\t} lane[8];\n+\tu8 res5[0x19fc - 0xa00];\n+};\n+\n #endif /*__ASSEMBLY__*/\n #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\nindex ea8aced..697f072 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h\n@@ -121,6 +121,7 @@ int setup_chip_volt(void);\n /* Setup core vdd in unit mV */\n int board_setup_core_volt(u32 vdd);\n #endif\n+void ddr_enable_0v9_volt(bool en);\n \n void cpu_name(char *name);\n #ifdef CONFIG_SYS_FSL_ERRATUM_A009635\n", "prefixes": [ "U-Boot", "RESEND", "v3", "1/7" ] }