[{"id":1768836,"web_url":"http://patchwork.ozlabs.org/comment/1768836/","msgid":"","list_archive_url":null,"date":"2017-09-14T21:02:35","subject":"Re: [U-Boot] [RESEND PATCH v3 1/7] armv8: lsch3: Add serdes and DDR\n\tvoltage setup","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"You have a lot of magic numbers and delays. See inline comments.\n\nOn 09/03/2017 11:24 PM, Rajesh Bhagat wrote:\n> Adds SERDES voltage and reset SERDES lanes API and makes\n> enable/disable DDR controller support 0.9V API common.\n> \n> Signed-off-by: Ashish Kumar \n> Signed-off-by: Rajesh Bhagat \n> ---\n> Changes in v3:\n> Restructured LS1088A VID support to use common VID driver\n> Cosmetic review comments fixed\n> Added __iomem for accessing registers\n> \n> Changes in v2:\n> Checkpatch errors fixed\n> \n> .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 274 +++++++++++++++++++++\n> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 34 +--\n> .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-\n> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++\n> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +\n> 5 files changed, 327 insertions(+), 18 deletions(-)\n> \n> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> index 179cac6..39f2cdf 100644\n> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> @@ -158,6 +158,280 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,\n> \tserdes_prtcl_map[NONE] = 1;\n> }\n> \n> +__weak int get_serdes_volt(void)\n> +{\n> +\treturn -1;\n> +}\n> +\n> +__weak int set_serdes_volt(int svdd)\n> +{\n> +\treturn -1;\n> +}\n> +\n> +int setup_serdes_volt(u32 svdd)\n> +{\n> +\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n> +\tstruct ccsr_serdes __iomem *serdes1_base;\n> +\tu32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tstruct ccsr_serdes __iomem *serdes2_base;\n> +\tu32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);\n> +#endif\n> +\tu32 cfg_tmp, reg = 0;\n> +\tint svdd_cur, svdd_tar;\n> +\tint ret = 1;\n> +\tint i;\n> +\n> +\t/* Only support switch SVDD to 900mV */\n> +\tif (svdd != 900)\n> +\t\treturn -1;\n> +\n> +\t/* Scale up to the LTC resolution is 1/4096V */\n> +\tsvdd = (svdd * 4096) / 1000;\n> +\n> +\tsvdd_tar = svdd;\n> +\tsvdd_cur = get_serdes_volt();\n> +\tif (svdd_cur < 0)\n> +\t\treturn -EINVAL;\n> +\n> +\tdebug(\"%s: current SVDD: %x; target SVDD: %x\\n\",\n> +\t __func__, svdd_cur, svdd_tar);\n> +\tif (svdd_cur == svdd_tar)\n> +\t\treturn 0;\n> +\n> +\tserdes1_base = (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tserdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);\n> +#endif\n> +\n> +\t/* Put the all enabled lanes in reset */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n> +\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n> +\n> +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> +\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n> +\t\treg &= 0xFF9FFFFF;\n> +\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n> +\t}\n> +#endif\n\nPlease use local macros instead of magic numbers here and below.\n\n> +\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n> +\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n> +\n> +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> +\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n> +\t\treg &= 0xFF9FFFFF;\n> +\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n> +\t}\n> +#endif\n> +\n> +\t/* Put the all enabled PLL in reset */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\treg &= 0xFFFFFFBF;\n> +\t\treg |= 0x10000000;\n> +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t}\n> +\tudelay(1);\n> +\n> +\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\treg &= 0xFFFFFF1F;\n> +\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +#endif\n> +\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> +\tcfg_tmp >>= 2;\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\treg &= 0xFFFFFFBF;\n> +\t\treg |= 0x10000000;\n> +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t}\n> +\tudelay(1);\n\nWhat's this delay for?\n\n> +\n> +\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\treg &= 0xFFFFFF1F;\n> +\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +#endif\n> +\n> +\t/* Put the Rx/Tx calibration into reset */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\treg = in_le32(&serdes1_base->srdstcalcr);\n> +\treg &= 0xF7FFFFFF;\n> +\tout_le32(&serdes1_base->srdstcalcr, reg);\n> +\treg = in_le32(&serdes1_base->srdsrcalcr);\n> +\treg &= 0xF7FFFFFF;\n> +\tout_le32(&serdes1_base->srdsrcalcr, reg);\n> +#endif\n> +\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\treg = in_le32(&serdes2_base->srdstcalcr);\n> +\treg &= 0xF7FFFFFF;\n> +\tout_le32(&serdes2_base->srdstcalcr, reg);\n> +\treg = in_le32(&serdes2_base->srdsrcalcr);\n> +\treg &= 0xF7FFFFFF;\n> +\tout_le32(&serdes2_base->srdsrcalcr, reg);\n> +#endif\n> +\n> +\tret = set_serdes_volt(svdd);\n> +\tif (ret < 0) {\n> +\t\tprintf(\"could not change SVDD\\n\");\n> +\t\tret = -1;\n> +\t}\n> +\n> +\t/* For each PLL that’s not disabled via RCW enable the SERDES */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\treg |= 0x00000020;\n> +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t\tudelay(1);\n\nWhy delay here?\n\n> +\n> +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\treg |= 0x00000080;\n> +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t\tudelay(1);\n\nHere.\n\n> +\t\t/* Take the Rx/Tx calibration out of reset */\n> +\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n> +\t\t\tudelay(1);\n> +\t\t\treg = in_le32(&serdes1_base->srdstcalcr);\n> +\t\t\treg |= 0x08000000;\n> +\t\t\tout_le32(&serdes1_base->srdstcalcr, reg);\n> +\t\t\treg = in_le32(&serdes1_base->srdsrcalcr);\n> +\t\t\treg |= 0x08000000;\n> +\t\t\tout_le32(&serdes1_base->srdsrcalcr, reg);\n> +\t\t}\n> +\t\tudelay(1);\n\nWhy delay here?\n\n> +\t}\n> +#endif\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> +\tcfg_tmp >>= 2;\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\treg |= 0x00000020;\n> +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t\tudelay(1);\n> +\n> +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\treg |= 0x00000080;\n> +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t\tudelay(1);\n> +\n> +\t\t/* Take the Rx/Tx calibration out of reset */\n> +\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n> +\t\t\tudelay(1);\n> +\t\t\treg = in_le32(&serdes2_base->srdstcalcr);\n> +\t\t\treg |= 0x08000000;\n> +\t\t\tout_le32(&serdes2_base->srdstcalcr, reg);\n> +\t\t\treg = in_le32(&serdes2_base->srdsrcalcr);\n> +\t\t\treg |= 0x08000000;\n> +\t\t\tout_le32(&serdes2_base->srdsrcalcr, reg);\n> +\t\t}\n> +\t\tudelay(1);\n> +\t}\n> +#endif\n\nYou have many duplicated code. Use functions or macros.\n\n> +\n> +\t/* Wait for at atleast 625us, ensure the PLLs being reset are locked */\n> +\tudelay(800);\n\nYou said 625us, but using 800.\n\n> +\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\t/* if the PLL is not locked, set RST_ERR */\n> +\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n> +\t\tif (!((reg >> 23) & 0x1)) {\n> +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\t\treg |= 0x20000000;\n> +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t\t} else {\n> +\t\t\tudelay(1);\n> +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\t\treg &= 0xFFFFFFEF;\n> +\t\t\treg |= 0x00000040;\n> +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t\t\tudelay(1);\n> +\t\t}\n> +\t}\n> +#endif\n> +\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> +\tcfg_tmp >>= 2;\n> +\n> +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> +\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n> +\t\tif (!((reg >> 23) & 0x1)) {\n> +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\t\treg |= 0x20000000;\n> +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t\t} else {\n> +\t\t\tudelay(1);\n> +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\t\treg &= 0xFFFFFFEF;\n> +\t\t\treg |= 0x00000040;\n> +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t\t\tudelay(1);\n> +\t\t}\n> +\t}\n> +#endif\n> +\t/* Take the all enabled lanes out of reset */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n> +\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n> +\n> +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> +\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n> +\t\treg |= 0x00600000;\n> +\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n> +\t}\n> +#endif\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n> +\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n> +\n> +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> +\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n> +\t\treg |= 0x00600000;\n> +\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n> +\t}\n> +#endif\n> +\n> +\t/* For each PLL being reset, and achieved PLL lock set RST_DONE */\n> +#ifdef CONFIG_SYS_FSL_SRDS_1\n> +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> +\tfor (i = 0; i < 2; i++) {\n> +\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n> +\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n> +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> +\t\t\treg |= 0x40000000;\n> +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> +\t\t}\n> +\t}\n> +#endif\n> +#ifdef CONFIG_SYS_FSL_SRDS_2\n> +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> +\tcfg_tmp >>= 2;\n> +\n> +\tfor (i = 0; i < 2; i++) {\n> +\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n> +\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n> +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> +\t\t\treg |= 0x40000000;\n> +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> +\t\t}\n> +\t}\n> +#endif\n> +\n> +\treturn ret;\n> +}\n> +\n> void fsl_serdes_init(void)\n> {\n> #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)\n> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> index 83e2871..4e96c7b 100644\n> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> @@ -404,23 +404,6 @@ static int setup_core_volt(u32 vdd)\n> \treturn board_setup_core_volt(vdd);\n> }\n> \n> -#ifdef CONFIG_SYS_FSL_DDR\n> -static void ddr_enable_0v9_volt(bool en)\n> -{\n> -\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n> -\tu32 tmp;\n> -\n> -\ttmp = ddr_in32(&ddr->ddr_cdr1);\n> -\n> -\tif (en)\n> -\t\ttmp |= DDR_CDR1_V0PT9_EN;\n> -\telse\n> -\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n> -\n> -\tddr_out32(&ddr->ddr_cdr1, tmp);\n> -}\n> -#endif\n> -\n> int setup_chip_volt(void)\n> {\n> \tint vdd;\n> @@ -485,6 +468,23 @@ void fsl_lsch2_early_init_f(void)\n> }\n> #endif\n> \n> +#ifdef CONFIG_SYS_FSL_DDR\n> +void ddr_enable_0v9_volt(bool en)\n> +{\n> +\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n> +\tu32 tmp;\n> +\n> +\ttmp = ddr_in32(&ddr->ddr_cdr1);\n> +\n> +\tif (en)\n> +\t\ttmp |= DDR_CDR1_V0PT9_EN;\n> +\telse\n> +\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n> +\n> +\tddr_out32(&ddr->ddr_cdr1, tmp);\n> +}\n> +#endif\n> +\n\n\nI lost track. When do you use 0.9v for DDR?\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"h1R80S9U\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtWFj1XDfz9s7h\n\tfor ;\n\tFri, 15 Sep 2017 07:02:49 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid DC0B6C21EC1; Thu, 14 Sep 2017 21:02:44 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6A099C21D5B;\n\tThu, 14 Sep 2017 21:02:40 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 69395C21D5B; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1769896,"web_url":"http://patchwork.ozlabs.org/comment/1769896/","msgid":"","list_archive_url":null,"date":"2017-09-18T06:57:43","subject":"Re: [U-Boot] [RESEND PATCH v3 1/7] armv8: lsch3: Add serdes and DDR\n\tvoltage setup","submitter":{"id":68498,"url":"http://patchwork.ozlabs.org/api/people/68498/","name":"Rajesh Bhagat","email":"rajesh.bhagat@nxp.com"},"content":"> -----Original Message-----\n> From: York Sun\n> Sent: Friday, September 15, 2017 2:33 AM\n> To: Rajesh Bhagat ; u-boot@lists.denx.de\n> Cc: Prabhakar Kushwaha ; Ashish Kumar\n> \n> Subject: Re: [RESEND PATCH v3 1/7] armv8: lsch3: Add serdes and DDR voltage\n> setup\n> \n> You have a lot of magic numbers and delays. See inline comments.\n> \n> On 09/03/2017 11:24 PM, Rajesh Bhagat wrote:\n> > Adds SERDES voltage and reset SERDES lanes API and makes\n> > enable/disable DDR controller support 0.9V API common.\n> >\n> > Signed-off-by: Ashish Kumar \n> > Signed-off-by: Rajesh Bhagat \n> > ---\n> > Changes in v3:\n> > Restructured LS1088A VID support to use common VID driver\n> > Cosmetic review comments fixed\n> > Added __iomem for accessing registers\n> >\n> > Changes in v2:\n> > Checkpatch errors fixed\n> >\n> > .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 274\n> +++++++++++++++++++++\n> > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 34 +--\n> > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-\n> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++\n> > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +\n> > 5 files changed, 327 insertions(+), 18 deletions(-)\n> >\n> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> > index 179cac6..39f2cdf 100644\n> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c\n> > @@ -158,6 +158,280 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32\n> sd_prctl_mask,\n> > \tserdes_prtcl_map[NONE] = 1;\n> > }\n> >\n> > +__weak int get_serdes_volt(void)\n> > +{\n> > +\treturn -1;\n> > +}\n> > +\n> > +__weak int set_serdes_volt(int svdd)\n> > +{\n> > +\treturn -1;\n> > +}\n> > +\n> > +int setup_serdes_volt(u32 svdd)\n> > +{\n> > +\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n> > +\tstruct ccsr_serdes __iomem *serdes1_base;\n> > +\tu32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR -\n> > +1]); #ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tstruct ccsr_serdes __iomem *serdes2_base;\n> > +\tu32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR -\n> > +1]); #endif\n> > +\tu32 cfg_tmp, reg = 0;\n> > +\tint svdd_cur, svdd_tar;\n> > +\tint ret = 1;\n> > +\tint i;\n> > +\n> > +\t/* Only support switch SVDD to 900mV */\n> > +\tif (svdd != 900)\n> > +\t\treturn -1;\n> > +\n> > +\t/* Scale up to the LTC resolution is 1/4096V */\n> > +\tsvdd = (svdd * 4096) / 1000;\n> > +\n> > +\tsvdd_tar = svdd;\n> > +\tsvdd_cur = get_serdes_volt();\n> > +\tif (svdd_cur < 0)\n> > +\t\treturn -EINVAL;\n> > +\n> > +\tdebug(\"%s: current SVDD: %x; target SVDD: %x\\n\",\n> > +\t __func__, svdd_cur, svdd_tar);\n> > +\tif (svdd_cur == svdd_tar)\n> > +\t\treturn 0;\n> > +\n> > +\tserdes1_base = (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tserdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR +\n> > +0x10000); #endif\n> > +\n> > +\t/* Put the all enabled lanes in reset */ #ifdef\n> > +CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n> > +\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n> > +\n> > +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> > +\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n> > +\t\treg &= 0xFF9FFFFF;\n> > +\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n> > +\t}\n> > +#endif\n> \n> Please use local macros instead of magic numbers here and below.\n> \n\nWill take care in v3 \n\n> > +\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n> > +\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n> > +\n> > +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> > +\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n> > +\t\treg &= 0xFF9FFFFF;\n> > +\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n> > +\t}\n> > +#endif\n> > +\n> > +\t/* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\treg &= 0xFFFFFFBF;\n> > +\t\treg |= 0x10000000;\n> > +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t}\n> > +\tudelay(1);\n> > +\n> > +\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\treg &= 0xFFFFFF1F;\n> > +\tout_le32(&serdes1_base->bank[i].rstctl, reg); #endif\n> > +\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> > +\tcfg_tmp >>= 2;\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\treg &= 0xFFFFFFBF;\n> > +\t\treg |= 0x10000000;\n> > +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t}\n> > +\tudelay(1);\n> \n> What's this delay for?\n> \n\nThese delays are part of SERDES reset requirements, each step of \nSERDES reset requires some delay to be added.\n\n> > +\n> > +\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\treg &= 0xFFFFFF1F;\n> > +\tout_le32(&serdes2_base->bank[i].rstctl, reg); #endif\n> > +\n> > +\t/* Put the Rx/Tx calibration into reset */ #ifdef\n> > +CONFIG_SYS_FSL_SRDS_1\n> > +\treg = in_le32(&serdes1_base->srdstcalcr);\n> > +\treg &= 0xF7FFFFFF;\n> > +\tout_le32(&serdes1_base->srdstcalcr, reg);\n> > +\treg = in_le32(&serdes1_base->srdsrcalcr);\n> > +\treg &= 0xF7FFFFFF;\n> > +\tout_le32(&serdes1_base->srdsrcalcr, reg); #endif\n> > +\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\treg = in_le32(&serdes2_base->srdstcalcr);\n> > +\treg &= 0xF7FFFFFF;\n> > +\tout_le32(&serdes2_base->srdstcalcr, reg);\n> > +\treg = in_le32(&serdes2_base->srdsrcalcr);\n> > +\treg &= 0xF7FFFFFF;\n> > +\tout_le32(&serdes2_base->srdsrcalcr, reg); #endif\n> > +\n> > +\tret = set_serdes_volt(svdd);\n> > +\tif (ret < 0) {\n> > +\t\tprintf(\"could not change SVDD\\n\");\n> > +\t\tret = -1;\n> > +\t}\n> > +\n> > +\t/* For each PLL that's not disabled via RCW enable the SERDES */\n> > +#ifdef CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\treg |= 0x00000020;\n> > +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t\tudelay(1);\n> \n> Why delay here?\n> \n> > +\n> > +\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\treg |= 0x00000080;\n> > +\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t\tudelay(1);\n> \n> Here.\n> \n> > +\t\t/* Take the Rx/Tx calibration out of reset */\n> > +\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n> > +\t\t\tudelay(1);\n> > +\t\t\treg = in_le32(&serdes1_base->srdstcalcr);\n> > +\t\t\treg |= 0x08000000;\n> > +\t\t\tout_le32(&serdes1_base->srdstcalcr, reg);\n> > +\t\t\treg = in_le32(&serdes1_base->srdsrcalcr);\n> > +\t\t\treg |= 0x08000000;\n> > +\t\t\tout_le32(&serdes1_base->srdsrcalcr, reg);\n> > +\t\t}\n> > +\t\tudelay(1);\n> \n> Why delay here?\n> \n> > +\t}\n> > +#endif\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> > +\tcfg_tmp >>= 2;\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\treg |= 0x00000020;\n> > +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t\tudelay(1);\n> > +\n> > +\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\treg |= 0x00000080;\n> > +\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t\tudelay(1);\n> > +\n> > +\t\t/* Take the Rx/Tx calibration out of reset */\n> > +\t\tif (!(cfg_tmp == 0x3 && i == 1)) {\n> > +\t\t\tudelay(1);\n> > +\t\t\treg = in_le32(&serdes2_base->srdstcalcr);\n> > +\t\t\treg |= 0x08000000;\n> > +\t\t\tout_le32(&serdes2_base->srdstcalcr, reg);\n> > +\t\t\treg = in_le32(&serdes2_base->srdsrcalcr);\n> > +\t\t\treg |= 0x08000000;\n> > +\t\t\tout_le32(&serdes2_base->srdsrcalcr, reg);\n> > +\t\t}\n> > +\t\tudelay(1);\n> > +\t}\n> > +#endif\n> \n> You have many duplicated code. Use functions or macros.\n> \n\nWill take care in v3\n\n> > +\n> > +\t/* Wait for at atleast 625us, ensure the PLLs being reset are locked */\n> > +\tudelay(800);\n> \n> You said 625us, but using 800.\n> \n\nIt says atleast 625us, and delay is added for 800us. Again the SERDES requirement\nstates this. \n\n> > +\n> > +#ifdef CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\t/* if the PLL is not locked, set RST_ERR */\n> > +\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n> > +\t\tif (!((reg >> 23) & 0x1)) {\n> > +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\t\treg |= 0x20000000;\n> > +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t\t} else {\n> > +\t\t\tudelay(1);\n> > +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\t\treg &= 0xFFFFFFEF;\n> > +\t\t\treg |= 0x00000040;\n> > +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t\t\tudelay(1);\n> > +\t\t}\n> > +\t}\n> > +#endif\n> > +\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> > +\tcfg_tmp >>= 2;\n> > +\n> > +\tfor (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {\n> > +\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n> > +\t\tif (!((reg >> 23) & 0x1)) {\n> > +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\t\treg |= 0x20000000;\n> > +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t\t} else {\n> > +\t\t\tudelay(1);\n> > +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\t\treg &= 0xFFFFFFEF;\n> > +\t\t\treg |= 0x00000040;\n> > +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t\t\tudelay(1);\n> > +\t\t}\n> > +\t}\n> > +#endif\n> > +\t/* Take the all enabled lanes out of reset */ #ifdef\n> > +CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & FSL_CHASSIS3_SRDS1_PRTCL_MASK;\n> > +\tcfg_tmp >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n> > +\n> > +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> > +\t\treg = in_le32(&serdes1_base->lane[i].gcr0);\n> > +\t\treg |= 0x00600000;\n> > +\t\tout_le32(&serdes1_base->lane[i].gcr0, reg);\n> > +\t}\n> > +#endif\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds2 & FSL_CHASSIS3_SRDS2_PRTCL_MASK;\n> > +\tcfg_tmp >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;\n> > +\n> > +\tfor (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {\n> > +\t\treg = in_le32(&serdes2_base->lane[i].gcr0);\n> > +\t\treg |= 0x00600000;\n> > +\t\tout_le32(&serdes2_base->lane[i].gcr0, reg);\n> > +\t}\n> > +#endif\n> > +\n> > +\t/* For each PLL being reset, and achieved PLL lock set RST_DONE */\n> > +#ifdef CONFIG_SYS_FSL_SRDS_1\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0x3;\n> > +\tfor (i = 0; i < 2; i++) {\n> > +\t\treg = in_le32(&serdes1_base->bank[i].pllcr0);\n> > +\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n> > +\t\t\treg = in_le32(&serdes1_base->bank[i].rstctl);\n> > +\t\t\treg |= 0x40000000;\n> > +\t\t\tout_le32(&serdes1_base->bank[i].rstctl, reg);\n> > +\t\t}\n> > +\t}\n> > +#endif\n> > +#ifdef CONFIG_SYS_FSL_SRDS_2\n> > +\tcfg_tmp = cfg_rcwsrds1 & 0xC;\n> > +\tcfg_tmp >>= 2;\n> > +\n> > +\tfor (i = 0; i < 2; i++) {\n> > +\t\treg = in_le32(&serdes2_base->bank[i].pllcr0);\n> > +\t\tif (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {\n> > +\t\t\treg = in_le32(&serdes2_base->bank[i].rstctl);\n> > +\t\t\treg |= 0x40000000;\n> > +\t\t\tout_le32(&serdes2_base->bank[i].rstctl, reg);\n> > +\t\t}\n> > +\t}\n> > +#endif\n> > +\n> > +\treturn ret;\n> > +}\n> > +\n> > void fsl_serdes_init(void)\n> > {\n> > #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) diff\n> > --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> > index 83e2871..4e96c7b 100644\n> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n> > @@ -404,23 +404,6 @@ static int setup_core_volt(u32 vdd)\n> > \treturn board_setup_core_volt(vdd);\n> > }\n> >\n> > -#ifdef CONFIG_SYS_FSL_DDR\n> > -static void ddr_enable_0v9_volt(bool en) -{\n> > -\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n> > -\tu32 tmp;\n> > -\n> > -\ttmp = ddr_in32(&ddr->ddr_cdr1);\n> > -\n> > -\tif (en)\n> > -\t\ttmp |= DDR_CDR1_V0PT9_EN;\n> > -\telse\n> > -\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n> > -\n> > -\tddr_out32(&ddr->ddr_cdr1, tmp);\n> > -}\n> > -#endif\n> > -\n> > int setup_chip_volt(void)\n> > {\n> > \tint vdd;\n> > @@ -485,6 +468,23 @@ void fsl_lsch2_early_init_f(void)\n> > }\n> > #endif\n> >\n> > +#ifdef CONFIG_SYS_FSL_DDR\n> > +void ddr_enable_0v9_volt(bool en)\n> > +{\n> > +\tstruct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;\n> > +\tu32 tmp;\n> > +\n> > +\ttmp = ddr_in32(&ddr->ddr_cdr1);\n> > +\n> > +\tif (en)\n> > +\t\ttmp |= DDR_CDR1_V0PT9_EN;\n> > +\telse\n> > +\t\ttmp &= ~DDR_CDR1_V0PT9_EN;\n> > +\n> > +\tddr_out32(&ddr->ddr_cdr1, tmp);\n> > +}\n> > +#endif\n> > +\n> \n> \n> I lost track. When do you use 0.9v for DDR?\n> \n\nWhen core voltage is set to 0.9v, it requires setting up the DDR controller \nwith 0.9 v setting. Prior to this patch, this code was used only in chasis2. \nMaking it non-static to use in chasis3 architecture also. \n\t\n> York","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"Qcf+U9Hs\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=rajesh.bhagat@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwcK44sMKz9s7G\n\tfor ;\n\tMon, 18 Sep 2017 16:57:59 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 27E04C21D70; Mon, 18 Sep 2017 06:57:53 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A631AC21D57;\n\tMon, 18 Sep 2017 06:57:48 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 18A42C21D57; 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