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GET /api/patches/808949/?format=api
{ "id": 808949, "url": "http://patchwork.ozlabs.org/api/patches/808949/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-13-thierry.reding@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170901185736.28051-13-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-01T18:57:32", "name": "[12/16] gpio: omap: Fix checkpatch warnings", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "85ebde9c8f1dd496e01f94e0d64bef4dd610eb27", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-13-thierry.reding@gmail.com/mbox/", "series": [ { "id": 1099, "url": "http://patchwork.ozlabs.org/api/series/1099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1099", "date": "2017-09-01T18:57:20", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1099/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/808949/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/808949/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"WiD4F1l2\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT5q1xD2z9sRW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 2 Sep 2017 04:58:06 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752379AbdIAS6E (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 1 Sep 2017 14:58:04 -0400", "from mail-wm0-f67.google.com ([74.125.82.67]:33748 \"EHLO\n\tmail-wm0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752547AbdIAS6C (ORCPT\n\t<rfc822; linux-tegra@vger.kernel.org>); Fri, 1 Sep 2017 14:58:02 -0400", "by mail-wm0-f67.google.com with SMTP id 187so742081wmn.0;\n\tFri, 01 Sep 2017 11:58:01 -0700 (PDT)", "from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id\n\tv2sm573566wrd.68.2017.09.01.11.57.59\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:57:59 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=A5tx/mHrm1dZazNGCfri1ib4FAyvHeEG5vQ3Tji7RGk=;\n\tb=WiD4F1l2PpRM7MFujeI7YmccQu53K4Yjljn/A2YmxpfatiZtH+XmId+U2ghUFg0tpP\n\tihDFaw8aTvixp7NdSqXRabAT6rMqGMfeKQ0OmRL33Bwt9C1UbcXQFU1wOwCen4/43f5x\n\tHJ0cwdDSxlH0DXrFw0T64XWUleh1mgDx2bP34U+1GPDrEagcivAmLHfIOy3Re4Xb80HU\n\tFsLWkKcZbCQ8aLqRzH0v8Nw4Bzoa1mzoA5nT7ftQvCQj0o2vLTt5SPE6RxpyGexey3ZN\n\tvQbDZTtj3y1rAK6QLiPrWW0aT7Cc96/6Myiwdt0b5qRhm6odyfs2KzTuLbEQQJG//3cR\n\tPeRQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=A5tx/mHrm1dZazNGCfri1ib4FAyvHeEG5vQ3Tji7RGk=;\n\tb=HQIM4iKQ5epTQfHIagsaOIFd1YIQU9PUi9VcEwKgA5tdAds79EPj/sX6eeQSYe0gq2\n\t0YgT2uDx6ARZAqteBRtSn2EbUVqSIx3q3IH1UX5LshbKh90U36CKSohHbmFc3fvlyeH2\n\tyP/JAeeXbHD1WoCBhehkF3ncjwY7PWdiVV3u4nqn4aVymSBtmnP0dwVHP890vhW1a7iS\n\tfXFxOvT3J790Mbk1aJX/CkixRaaTA+pUlL1eypWg97SR//95hdZO58UuChEY/9Xne35r\n\tmTeV4SIPZIp8UQxB9d1p6VGIezE5+R0Z8L39kOlDOkNdpGSYiebB7HeYew0//Up1tlnl\n\t61xA==", "X-Gm-Message-State": "AHPjjUi064maN57Ud5syDZU4INSlwww35pgHSim4+UaFWflFRNQOpn83\n\tpMa9bsLWtKgD+Q==", "X-Google-Smtp-Source": "ADKCNb5iRisDzZqU6/mVmau8OUqkJBkR1QYzIWyuMMSDuBJnBhvrAanJSjESrVFFG75I3+gaZRQ9Ww==", "X-Received": "by 10.28.73.212 with SMTP id w203mr946669wma.53.1504292280469;\n\tFri, 01 Sep 2017 11:58:00 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH 12/16] gpio: omap: Fix checkpatch warnings", "Date": "Fri, 1 Sep 2017 20:57:32 +0200", "Message-Id": "<20170901185736.28051-13-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170901185736.28051-1-thierry.reding@gmail.com>", "References": "<20170901185736.28051-1-thierry.reding@gmail.com>", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nUse unsigned int rather than unsigned, wrap lines longer than 80\ncharacters and other minor coding style cleanups.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpio-omap.c | 113 ++++++++++++++++++++++++++---------------------\n 1 file changed, 63 insertions(+), 50 deletions(-)", "diff": "diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c\nindex ce27d6a586bf..7c600cec3e44 100644\n--- a/drivers/gpio/gpio-omap.c\n+++ b/drivers/gpio/gpio-omap.c\n@@ -76,7 +76,8 @@ struct gpio_bank {\n \tint power_mode;\n \tbool workaround_enabled;\n \n-\tvoid (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);\n+\tvoid (*set_dataout)(struct gpio_bank *bank, unsigned int gpio,\n+\t\t\t int enable);\n \tint (*get_context_loss_count)(struct device *dev);\n \n \tstruct omap_gpio_reg_offs *regs;\n@@ -92,6 +93,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d);\n static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)\n {\n \tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n+\n \treturn gpiochip_get_data(chip);\n }\n \n@@ -113,8 +115,8 @@ static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,\n \n \n /* set data out value using dedicate set/clear register */\n-static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,\n-\t\t\t\t int enable)\n+static void omap_set_gpio_dataout_reg(struct gpio_bank *bank,\n+\t\t\t\t unsigned int offset, int enable)\n {\n \tvoid __iomem *reg = bank->base;\n \tu32 l = BIT(offset);\n@@ -131,8 +133,8 @@ static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,\n }\n \n /* set data out value using mask register */\n-static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,\n-\t\t\t\t int enable)\n+static void omap_set_gpio_dataout_mask(struct gpio_bank *bank,\n+\t\t\t\t unsigned int offset, int enable)\n {\n \tvoid __iomem *reg = bank->base + bank->regs->dataout;\n \tu32 gpio_bit = BIT(offset);\n@@ -161,7 +163,8 @@ static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)\n \treturn (readl_relaxed(reg) & (BIT(offset))) != 0;\n }\n \n-static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)\n+static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask,\n+\t\t\t\t bool set)\n {\n \tint l = readl_relaxed(base + reg);\n \n@@ -211,8 +214,8 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)\n *\n * Return: 0 on success, negative error otherwise.\n */\n-static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,\n-\t\t\t\t unsigned debounce)\n+static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned int offset,\n+\t\t\t\t unsigned int debounce)\n {\n \tvoid __iomem\t\t*reg;\n \tu32\t\t\tval;\n@@ -272,7 +275,8 @@ static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,\n * time too. The debounce clock will also be disabled when calling this function\n * if this is the only gpio in the bank using debounce.\n */\n-static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n+static void omap_clear_gpio_debounce(struct gpio_bank *bank,\n+\t\t\t\t unsigned int offset)\n {\n \tu32 gpio_bit = BIT(offset);\n \n@@ -284,8 +288,8 @@ static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n \n \tbank->dbck_enable_mask &= ~gpio_bit;\n \tbank->context.debounce_en &= ~gpio_bit;\n- writel_relaxed(bank->context.debounce_en,\n-\t\t bank->base + bank->regs->debounce_en);\n+\twritel_relaxed(bank->context.debounce_en,\n+\t\t bank->base + bank->regs->debounce_en);\n \n \tif (!bank->dbck_enable_mask) {\n \t\tbank->context.debounce = 0;\n@@ -297,7 +301,7 @@ static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n }\n \n static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,\n-\t\t\t\t\t\tunsigned trigger)\n+\t\t\t\t\t unsigned int trigger)\n {\n \tvoid __iomem *base = bank->base;\n \tu32 gpio_bit = BIT(gpio);\n@@ -321,7 +325,8 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,\n \t\t\treadl_relaxed(bank->base + bank->regs->fallingdetect);\n \n \tif (likely(!(bank->non_wakeup_gpios & gpio_bit))) {\n-\t\tomap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);\n+\t\tomap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit,\n+\t\t\t trigger != 0);\n \t\tbank->context.wake_en =\n \t\t\treadl_relaxed(bank->base + bank->regs->wkup_en);\n \t}\n@@ -376,11 +381,13 @@ static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)\n \twritel_relaxed(l, reg);\n }\n #else\n-static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}\n+static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)\n+{\n+}\n #endif\n \n static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,\n-\t\t\t\t unsigned trigger)\n+\t\t\t\t unsigned int trigger)\n {\n \tvoid __iomem *reg = bank->base;\n \tvoid __iomem *base = bank->base;\n@@ -425,7 +432,7 @@ static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,\n \treturn 0;\n }\n \n-static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)\n+static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned int offset)\n {\n \tif (bank->regs->pinctrl) {\n \t\tvoid __iomem *reg = bank->base + bank->regs->pinctrl;\n@@ -446,7 +453,8 @@ static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)\n \t}\n }\n \n-static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)\n+static void omap_disable_gpio_module(struct gpio_bank *bank,\n+\t\t\t\t unsigned int offset)\n {\n \tvoid __iomem *base = bank->base;\n \n@@ -471,14 +479,14 @@ static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)\n \t}\n }\n \n-static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)\n+static int omap_gpio_is_input(struct gpio_bank *bank, unsigned int offset)\n {\n \tvoid __iomem *reg = bank->base + bank->regs->direction;\n \n \treturn readl_relaxed(reg) & BIT(offset);\n }\n \n-static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)\n+static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned int offset)\n {\n \tif (!LINE_USED(bank->mod_usage, offset)) {\n \t\tomap_enable_gpio_module(bank, offset);\n@@ -487,12 +495,12 @@ static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)\n \tbank->irq_usage |= BIT(offset);\n }\n \n-static int omap_gpio_irq_type(struct irq_data *d, unsigned type)\n+static int omap_gpio_irq_type(struct irq_data *d, unsigned int type)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n \tint retval;\n \tunsigned long flags;\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \n \tif (type & ~IRQ_TYPE_SENSE_MASK)\n \t\treturn -EINVAL;\n@@ -544,7 +552,7 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)\n }\n \n static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,\n-\t\t\t\t\t unsigned offset)\n+\t\t\t\t\t unsigned int offset)\n {\n \tomap_clear_gpio_irqbank(bank, BIT(offset));\n }\n@@ -608,7 +616,7 @@ static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)\n }\n \n static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,\n-\t\t\t\t\t unsigned offset, int enable)\n+\t\t\t\t\t unsigned int offset, int enable)\n {\n \tif (enable)\n \t\tomap_enable_gpio_irqbank(bank, BIT(offset));\n@@ -624,7 +632,7 @@ static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)\n \treturn irq_set_irq_wake(bank->irq, enable);\n }\n \n-static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)\n+static int omap_gpio_request(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct gpio_bank *bank = gpiochip_get_data(chip);\n \tunsigned long flags;\n@@ -644,7 +652,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)\n \treturn 0;\n }\n \n-static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)\n+static void omap_gpio_free(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct gpio_bank *bank = gpiochip_get_data(chip);\n \tunsigned long flags;\n@@ -702,9 +710,11 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n \t\tif (bank->level_mask)\n \t\t\tlevel_mask = bank->level_mask & enabled;\n \n-\t\t/* clear edge sensitive interrupts before handler(s) are\n-\t\tcalled so that we don't miss any interrupt occurred while\n-\t\texecuting them */\n+\t\t/*\n+\t\t * clear edge sensitive interrupts before handler(s) are\n+\t\t * called so that we don't miss any interrupt occurred while\n+\t\t * executing them\n+\t\t */\n \t\tomap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);\n \t\tomap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);\n \t\tomap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);\n@@ -715,6 +725,8 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n \t\t\tbreak;\n \n \t\twhile (isr) {\n+\t\t\tunsigned int irq;\n+\n \t\t\tbit = __ffs(isr);\n \t\t\tisr &= ~(BIT(bit));\n \n@@ -733,8 +745,8 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n \n \t\t\traw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);\n \n-\t\t\tgeneric_handle_irq(irq_find_mapping(bank->chip.irq.domain,\n-\t\t\t\t\t\t\t bit));\n+\t\t\tirq = irq_find_mapping(bank->chip.irq.domain, bit);\n+\t\t\tgeneric_handle_irq(irq);\n \n \t\t\traw_spin_unlock_irqrestore(&bank->wa_lock,\n \t\t\t\t\t\t wa_lock_flags);\n@@ -749,7 +761,7 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n \tunsigned long flags;\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \n \traw_spin_lock_irqsave(&bank->lock, flags);\n \n@@ -773,7 +785,7 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n \tunsigned long flags;\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \n \traw_spin_lock_irqsave(&bank->lock, flags);\n \tbank->irq_usage &= ~(BIT(offset));\n@@ -809,7 +821,7 @@ static void gpio_irq_bus_sync_unlock(struct irq_data *data)\n static void omap_gpio_ack_irq(struct irq_data *d)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \n \tomap_clear_gpio_irqstatus(bank, offset);\n }\n@@ -817,7 +829,7 @@ static void omap_gpio_ack_irq(struct irq_data *d)\n static void omap_gpio_mask_irq(struct irq_data *d)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \tunsigned long flags;\n \n \traw_spin_lock_irqsave(&bank->lock, flags);\n@@ -829,7 +841,7 @@ static void omap_gpio_mask_irq(struct irq_data *d)\n static void omap_gpio_unmask_irq(struct irq_data *d)\n {\n \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n-\tunsigned offset = d->hwirq;\n+\tunsigned int offset = d->hwirq;\n \tu32 trigger = irqd_get_trigger_type(d);\n \tunsigned long flags;\n \n@@ -837,8 +849,10 @@ static void omap_gpio_unmask_irq(struct irq_data *d)\n \tif (trigger)\n \t\tomap_set_gpio_triggering(bank, offset, trigger);\n \n-\t/* For level-triggered GPIOs, the clearing must be done after\n-\t * the HW source is cleared, thus after the handler has run */\n+\t/*\n+\t * For level-triggered GPIOs, the clearing must be done after\n+\t * the HW source is cleared, thus after the handler has run\n+\t */\n \tif (bank->level_mask & BIT(offset)) {\n \t\tomap_set_gpio_irqenable(bank, offset, 0);\n \t\tomap_clear_gpio_irqstatus(bank, offset);\n@@ -912,7 +926,7 @@ static inline void omap_mpuio_init(struct gpio_bank *bank)\n \n /*---------------------------------------------------------------------*/\n \n-static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)\n+static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct gpio_bank *bank;\n \tunsigned long flags;\n@@ -927,7 +941,7 @@ static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)\n \treturn dir;\n }\n \n-static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)\n+static int omap_gpio_input(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct gpio_bank *bank;\n \tunsigned long flags;\n@@ -939,7 +953,7 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)\n \treturn 0;\n }\n \n-static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)\n+static int omap_gpio_get(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct gpio_bank *bank;\n \n@@ -951,7 +965,8 @@ static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)\n \t\treturn omap_get_gpio_dataout(bank, offset);\n }\n \n-static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)\n+static int omap_gpio_output(struct gpio_chip *chip, unsigned int offset,\n+\t\t\t int value)\n {\n \tstruct gpio_bank *bank;\n \tunsigned long flags;\n@@ -964,8 +979,8 @@ static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)\n \treturn 0;\n }\n \n-static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,\n-\t\t\t unsigned debounce)\n+static int omap_gpio_debounce(struct gpio_chip *chip, unsigned int offset,\n+\t\t\t unsigned int debounce)\n {\n \tstruct gpio_bank *bank;\n \tunsigned long flags;\n@@ -985,7 +1000,7 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,\n \treturn ret;\n }\n \n-static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,\n+static int omap_gpio_set_config(struct gpio_chip *chip, unsigned int offset,\n \t\t\t\tunsigned long config)\n {\n \tu32 debounce;\n@@ -997,7 +1012,8 @@ static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,\n \treturn omap_gpio_debounce(chip, offset, debounce);\n }\n \n-static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)\n+static void omap_gpio_set(struct gpio_chip *chip, unsigned int offset,\n+\t\t\t int value)\n {\n \tstruct gpio_bank *bank;\n \tunsigned long flags;\n@@ -1153,10 +1169,8 @@ static int omap_gpio_probe(struct platform_device *pdev)\n \t\treturn -EINVAL;\n \n \tbank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);\n-\tif (!bank) {\n-\t\tdev_err(dev, \"Memory alloc failed\\n\");\n+\tif (!bank)\n \t\treturn -ENOMEM;\n-\t}\n \n \tirqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);\n \tif (!irqc)\n@@ -1217,9 +1231,8 @@ static int omap_gpio_probe(struct platform_device *pdev)\n \t/* Static mapping, never released */\n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n \tbank->base = devm_ioremap_resource(dev, res);\n-\tif (IS_ERR(bank->base)) {\n+\tif (IS_ERR(bank->base))\n \t\treturn PTR_ERR(bank->base);\n-\t}\n \n \tif (bank->dbck_flag) {\n \t\tbank->dbck = devm_clk_get(dev, \"dbclk\");\n", "prefixes": [ "12/16" ] }