[{"id":1769494,"web_url":"http://patchwork.ozlabs.org/comment/1769494/","msgid":"<33c75022-080e-fe25-5b26-7f1331d62740@ti.com>","list_archive_url":null,"date":"2017-09-15T22:23:09","subject":"Re: [PATCH 12/16] gpio: omap: Fix checkpatch warnings","submitter":{"id":25084,"url":"http://patchwork.ozlabs.org/api/people/25084/","name":"Grygorii Strashko","email":"grygorii.strashko@ti.com"},"content":"On 09/01/2017 01:57 PM, Thierry Reding wrote:\n> From: Thierry Reding <treding@nvidia.com>\n> \n> Use unsigned int rather than unsigned, wrap lines longer than 80\n> characters and other minor coding style cleanups.\n> \n> Signed-off-by: Thierry Reding <treding@nvidia.com>\n\nI think it can be separated from this series.\nAcked-by: Grygorii Strashko <grygorii.strashko@ti.com>\n\n> ---\n>   drivers/gpio/gpio-omap.c | 113 ++++++++++++++++++++++++++---------------------\n>   1 file changed, 63 insertions(+), 50 deletions(-)\n> \n> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c\n> index ce27d6a586bf..7c600cec3e44 100644\n> --- a/drivers/gpio/gpio-omap.c\n> +++ b/drivers/gpio/gpio-omap.c\n> @@ -76,7 +76,8 @@ struct gpio_bank {\n>   \tint power_mode;\n>   \tbool workaround_enabled;\n>   \n> -\tvoid (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);\n> +\tvoid (*set_dataout)(struct gpio_bank *bank, unsigned int gpio,\n> +\t\t\t    int enable);\n>   \tint (*get_context_loss_count)(struct device *dev);\n>   \n>   \tstruct omap_gpio_reg_offs *regs;\n> @@ -92,6 +93,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d);\n>   static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)\n>   {\n>   \tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n> +\n>   \treturn gpiochip_get_data(chip);\n>   }\n>   \n> @@ -113,8 +115,8 @@ static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,\n>   \n>   \n>   /* set data out value using dedicate set/clear register */\n> -static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,\n> -\t\t\t\t      int enable)\n> +static void omap_set_gpio_dataout_reg(struct gpio_bank *bank,\n> +\t\t\t\t      unsigned int offset, int enable)\n>   {\n>   \tvoid __iomem *reg = bank->base;\n>   \tu32 l = BIT(offset);\n> @@ -131,8 +133,8 @@ static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,\n>   }\n>   \n>   /* set data out value using mask register */\n> -static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,\n> -\t\t\t\t       int enable)\n> +static void omap_set_gpio_dataout_mask(struct gpio_bank *bank,\n> +\t\t\t\t       unsigned int offset, int enable)\n>   {\n>   \tvoid __iomem *reg = bank->base + bank->regs->dataout;\n>   \tu32 gpio_bit = BIT(offset);\n> @@ -161,7 +163,8 @@ static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)\n>   \treturn (readl_relaxed(reg) & (BIT(offset))) != 0;\n>   }\n>   \n> -static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)\n> +static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask,\n> +\t\t\t\t bool set)\n>   {\n>   \tint l = readl_relaxed(base + reg);\n>   \n> @@ -211,8 +214,8 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)\n>    *\n>    * Return: 0 on success, negative error otherwise.\n>    */\n> -static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,\n> -\t\t\t\t   unsigned debounce)\n> +static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned int offset,\n> +\t\t\t\t   unsigned int debounce)\n>   {\n>   \tvoid __iomem\t\t*reg;\n>   \tu32\t\t\tval;\n> @@ -272,7 +275,8 @@ static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,\n>    * time too. The debounce clock will also be disabled when calling this function\n>    * if this is the only gpio in the bank using debounce.\n>    */\n> -static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n> +static void omap_clear_gpio_debounce(struct gpio_bank *bank,\n> +\t\t\t\t     unsigned int offset)\n>   {\n>   \tu32 gpio_bit = BIT(offset);\n>   \n> @@ -284,8 +288,8 @@ static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n>   \n>   \tbank->dbck_enable_mask &= ~gpio_bit;\n>   \tbank->context.debounce_en &= ~gpio_bit;\n> -        writel_relaxed(bank->context.debounce_en,\n> -\t\t     bank->base + bank->regs->debounce_en);\n> +\twritel_relaxed(bank->context.debounce_en,\n> +\t\t       bank->base + bank->regs->debounce_en);\n>   \n>   \tif (!bank->dbck_enable_mask) {\n>   \t\tbank->context.debounce = 0;\n> @@ -297,7 +301,7 @@ static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)\n>   }\n>   \n>   static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,\n> -\t\t\t\t\t\tunsigned trigger)\n> +\t\t\t\t\t unsigned int trigger)\n>   {\n>   \tvoid __iomem *base = bank->base;\n>   \tu32 gpio_bit = BIT(gpio);\n> @@ -321,7 +325,8 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,\n>   \t\t\treadl_relaxed(bank->base + bank->regs->fallingdetect);\n>   \n>   \tif (likely(!(bank->non_wakeup_gpios & gpio_bit))) {\n> -\t\tomap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);\n> +\t\tomap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit,\n> +\t\t\t      trigger != 0);\n>   \t\tbank->context.wake_en =\n>   \t\t\treadl_relaxed(bank->base + bank->regs->wkup_en);\n>   \t}\n> @@ -376,11 +381,13 @@ static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)\n>   \twritel_relaxed(l, reg);\n>   }\n>   #else\n> -static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}\n> +static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)\n> +{\n> +}\n>   #endif\n>   \n>   static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,\n> -\t\t\t\t    unsigned trigger)\n> +\t\t\t\t    unsigned int trigger)\n>   {\n>   \tvoid __iomem *reg = bank->base;\n>   \tvoid __iomem *base = bank->base;\n> @@ -425,7 +432,7 @@ static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,\n>   \treturn 0;\n>   }\n>   \n> -static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)\n> +static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned int offset)\n>   {\n>   \tif (bank->regs->pinctrl) {\n>   \t\tvoid __iomem *reg = bank->base + bank->regs->pinctrl;\n> @@ -446,7 +453,8 @@ static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)\n>   \t}\n>   }\n>   \n> -static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)\n> +static void omap_disable_gpio_module(struct gpio_bank *bank,\n> +\t\t\t\t     unsigned int offset)\n>   {\n>   \tvoid __iomem *base = bank->base;\n>   \n> @@ -471,14 +479,14 @@ static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)\n>   \t}\n>   }\n>   \n> -static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)\n> +static int omap_gpio_is_input(struct gpio_bank *bank, unsigned int offset)\n>   {\n>   \tvoid __iomem *reg = bank->base + bank->regs->direction;\n>   \n>   \treturn readl_relaxed(reg) & BIT(offset);\n>   }\n>   \n> -static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)\n> +static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned int offset)\n>   {\n>   \tif (!LINE_USED(bank->mod_usage, offset)) {\n>   \t\tomap_enable_gpio_module(bank, offset);\n> @@ -487,12 +495,12 @@ static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)\n>   \tbank->irq_usage |= BIT(offset);\n>   }\n>   \n> -static int omap_gpio_irq_type(struct irq_data *d, unsigned type)\n> +static int omap_gpio_irq_type(struct irq_data *d, unsigned int type)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n>   \tint retval;\n>   \tunsigned long flags;\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \n>   \tif (type & ~IRQ_TYPE_SENSE_MASK)\n>   \t\treturn -EINVAL;\n> @@ -544,7 +552,7 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)\n>   }\n>   \n>   static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,\n> -\t\t\t\t\t     unsigned offset)\n> +\t\t\t\t\t     unsigned int offset)\n>   {\n>   \tomap_clear_gpio_irqbank(bank, BIT(offset));\n>   }\n> @@ -608,7 +616,7 @@ static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)\n>   }\n>   \n>   static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,\n> -\t\t\t\t\t   unsigned offset, int enable)\n> +\t\t\t\t\t   unsigned int offset, int enable)\n>   {\n>   \tif (enable)\n>   \t\tomap_enable_gpio_irqbank(bank, BIT(offset));\n> @@ -624,7 +632,7 @@ static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)\n>   \treturn irq_set_irq_wake(bank->irq, enable);\n>   }\n>   \n> -static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)\n> +static int omap_gpio_request(struct gpio_chip *chip, unsigned int offset)\n>   {\n>   \tstruct gpio_bank *bank = gpiochip_get_data(chip);\n>   \tunsigned long flags;\n> @@ -644,7 +652,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)\n>   \treturn 0;\n>   }\n>   \n> -static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)\n> +static void omap_gpio_free(struct gpio_chip *chip, unsigned int offset)\n>   {\n>   \tstruct gpio_bank *bank = gpiochip_get_data(chip);\n>   \tunsigned long flags;\n> @@ -702,9 +710,11 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n>   \t\tif (bank->level_mask)\n>   \t\t\tlevel_mask = bank->level_mask & enabled;\n>   \n> -\t\t/* clear edge sensitive interrupts before handler(s) are\n> -\t\tcalled so that we don't miss any interrupt occurred while\n> -\t\texecuting them */\n> +\t\t/*\n> +\t\t * clear edge sensitive interrupts before handler(s) are\n> +\t\t * called so that we don't miss any interrupt occurred while\n> +\t\t * executing them\n> +\t\t */\n>   \t\tomap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);\n>   \t\tomap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);\n>   \t\tomap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);\n> @@ -715,6 +725,8 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n>   \t\t\tbreak;\n>   \n>   \t\twhile (isr) {\n> +\t\t\tunsigned int irq;\n> +\n>   \t\t\tbit = __ffs(isr);\n>   \t\t\tisr &= ~(BIT(bit));\n>   \n> @@ -733,8 +745,8 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)\n>   \n>   \t\t\traw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);\n>   \n> -\t\t\tgeneric_handle_irq(irq_find_mapping(bank->chip.irq.domain,\n> -\t\t\t\t\t\t\t    bit));\n> +\t\t\tirq = irq_find_mapping(bank->chip.irq.domain, bit);\n> +\t\t\tgeneric_handle_irq(irq);\n>   \n>   \t\t\traw_spin_unlock_irqrestore(&bank->wa_lock,\n>   \t\t\t\t\t\t   wa_lock_flags);\n> @@ -749,7 +761,7 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n>   \tunsigned long flags;\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \n>   \traw_spin_lock_irqsave(&bank->lock, flags);\n>   \n> @@ -773,7 +785,7 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n>   \tunsigned long flags;\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \n>   \traw_spin_lock_irqsave(&bank->lock, flags);\n>   \tbank->irq_usage &= ~(BIT(offset));\n> @@ -809,7 +821,7 @@ static void gpio_irq_bus_sync_unlock(struct irq_data *data)\n>   static void omap_gpio_ack_irq(struct irq_data *d)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \n>   \tomap_clear_gpio_irqstatus(bank, offset);\n>   }\n> @@ -817,7 +829,7 @@ static void omap_gpio_ack_irq(struct irq_data *d)\n>   static void omap_gpio_mask_irq(struct irq_data *d)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \tunsigned long flags;\n>   \n>   \traw_spin_lock_irqsave(&bank->lock, flags);\n> @@ -829,7 +841,7 @@ static void omap_gpio_mask_irq(struct irq_data *d)\n>   static void omap_gpio_unmask_irq(struct irq_data *d)\n>   {\n>   \tstruct gpio_bank *bank = omap_irq_data_get_bank(d);\n> -\tunsigned offset = d->hwirq;\n> +\tunsigned int offset = d->hwirq;\n>   \tu32 trigger = irqd_get_trigger_type(d);\n>   \tunsigned long flags;\n>   \n> @@ -837,8 +849,10 @@ static void omap_gpio_unmask_irq(struct irq_data *d)\n>   \tif (trigger)\n>   \t\tomap_set_gpio_triggering(bank, offset, trigger);\n>   \n> -\t/* For level-triggered GPIOs, the clearing must be done after\n> -\t * the HW source is cleared, thus after the handler has run */\n> +\t/*\n> +\t * For level-triggered GPIOs, the clearing must be done after\n> +\t * the HW source is cleared, thus after the handler has run\n> +\t */\n>   \tif (bank->level_mask & BIT(offset)) {\n>   \t\tomap_set_gpio_irqenable(bank, offset, 0);\n>   \t\tomap_clear_gpio_irqstatus(bank, offset);\n> @@ -912,7 +926,7 @@ static inline void omap_mpuio_init(struct gpio_bank *bank)\n>   \n>   /*---------------------------------------------------------------------*/\n>   \n> -static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)\n> +static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \tunsigned long flags;\n> @@ -927,7 +941,7 @@ static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)\n>   \treturn dir;\n>   }\n>   \n> -static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)\n> +static int omap_gpio_input(struct gpio_chip *chip, unsigned int offset)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \tunsigned long flags;\n> @@ -939,7 +953,7 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)\n>   \treturn 0;\n>   }\n>   \n> -static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)\n> +static int omap_gpio_get(struct gpio_chip *chip, unsigned int offset)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \n> @@ -951,7 +965,8 @@ static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)\n>   \t\treturn omap_get_gpio_dataout(bank, offset);\n>   }\n>   \n> -static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)\n> +static int omap_gpio_output(struct gpio_chip *chip, unsigned int offset,\n> +\t\t\t    int value)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \tunsigned long flags;\n> @@ -964,8 +979,8 @@ static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)\n>   \treturn 0;\n>   }\n>   \n> -static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,\n> -\t\t\t      unsigned debounce)\n> +static int omap_gpio_debounce(struct gpio_chip *chip, unsigned int offset,\n> +\t\t\t      unsigned int debounce)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \tunsigned long flags;\n> @@ -985,7 +1000,7 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,\n>   \treturn ret;\n>   }\n>   \n> -static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,\n> +static int omap_gpio_set_config(struct gpio_chip *chip, unsigned int offset,\n>   \t\t\t\tunsigned long config)\n>   {\n>   \tu32 debounce;\n> @@ -997,7 +1012,8 @@ static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,\n>   \treturn omap_gpio_debounce(chip, offset, debounce);\n>   }\n>   \n> -static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)\n> +static void omap_gpio_set(struct gpio_chip *chip, unsigned int offset,\n> +\t\t\t  int value)\n>   {\n>   \tstruct gpio_bank *bank;\n>   \tunsigned long flags;\n> @@ -1153,10 +1169,8 @@ static int omap_gpio_probe(struct platform_device *pdev)\n>   \t\treturn -EINVAL;\n>   \n>   \tbank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);\n> -\tif (!bank) {\n> -\t\tdev_err(dev, \"Memory alloc failed\\n\");\n> +\tif (!bank)\n>   \t\treturn -ENOMEM;\n> -\t}\n>   \n>   \tirqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);\n>   \tif (!irqc)\n> @@ -1217,9 +1231,8 @@ static int omap_gpio_probe(struct platform_device *pdev)\n>   \t/* Static mapping, never released */\n>   \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n>   \tbank->base = devm_ioremap_resource(dev, res);\n> -\tif (IS_ERR(bank->base)) {\n> +\tif (IS_ERR(bank->base))\n>   \t\treturn PTR_ERR(bank->base);\n> -\t}\n>   \n>   \tif (bank->dbck_flag) {\n>   \t\tbank->dbck = devm_clk_get(dev, \"dbclk\");\n>","headers":{"Return-Path":"<linux-tegra-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"VR8G6UuU\";\n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv90t5MZrz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 08:23:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751542AbdIOWX6 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 15 Sep 2017 18:23:58 -0400","from fllnx209.ext.ti.com ([198.47.19.16]:31302 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750871AbdIOWX5 (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 15 Sep 2017 18:23:57 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8FMNF8q025906; \n\tFri, 15 Sep 2017 17:23:15 -0500","from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8FMNAgU006014;\n\tFri, 15 Sep 2017 17:23:10 -0500","from [128.247.59.147] (128.247.59.147) by DLEE70.ent.ti.com\n\t(157.170.170.113) with Microsoft SMTP Server id 14.3.294.0;\n\tFri, 15 Sep 2017 17:23:09 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505514195;\n\tbh=Rv8J9avYNjEQPkGryF1Duu1kqgsUKYWydkc9tjuZ3R4=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=VR8G6UuUwHMnW1jt883jrQBLd5WuWxZJXgUdAfsRYdmchOzNh5llkAgehH0XIEyPY\n\tiFwInuFXBjGqoprYw6j/oUPQWjvlvx+iIWot/N2OzFDg4qU1RauplAYY7M3Cvy0BbL\n\trm3r9EazSlO+hc2WutKpUmGWZpC5qOiD+oAdtePA=","Subject":"Re: [PATCH 12/16] gpio: omap: Fix checkpatch warnings","To":"Thierry Reding <thierry.reding@gmail.com>,\n\tLinus Walleij <linus.walleij@linaro.org>","CC":"Jonathan Hunter <jonathanh@nvidia.com>,\n\t<linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>\n\t<20170901185736.28051-13-thierry.reding@gmail.com>","From":"Grygorii Strashko <grygorii.strashko@ti.com>","Message-ID":"<33c75022-080e-fe25-5b26-7f1331d62740@ti.com>","Date":"Fri, 15 Sep 2017 17:23:09 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170901185736.28051-13-thierry.reding@gmail.com>","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[128.247.59.147]","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-tegra.vger.kernel.org>","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]