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{
    "id": 808714,
    "url": "http://patchwork.ozlabs.org/api/patches/808714/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901145343.19890-4-thierry.reding@gmail.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170901145343.19890-4-thierry.reding@gmail.com>",
    "list_archive_url": null,
    "date": "2017-09-01T14:53:43",
    "name": "[4/4] clk: tegra: Fix sor1_out clock implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "758af3962fc97107e8efc78642d8fa3608896b83",
    "submitter": {
        "id": 26234,
        "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api",
        "name": "Thierry Reding",
        "email": "thierry.reding@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901145343.19890-4-thierry.reding@gmail.com/mbox/",
    "series": [
        {
            "id": 1041,
            "url": "http://patchwork.ozlabs.org/api/series/1041/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1041",
            "date": "2017-09-01T14:53:40",
            "name": "[1/4] dt-bindings: clock: tegra: Add sor1_out clock",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/1041/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/808714/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/808714/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-Received": "by 10.28.54.39 with SMTP id d39mr578738wma.195.1504277630116;\n\tFri, 01 Sep 2017 07:53:50 -0700 (PDT)",
        "From": "Thierry Reding <thierry.reding@gmail.com>",
        "To": "Michael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@codeaurora.org>",
        "Cc": "Peter De Schrijver <pdeschrijver@nvidia.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tlinux-clk@vger.kernel.org, linux-tegra@vger.kernel.org",
        "Subject": "[PATCH 4/4] clk: tegra: Fix sor1_out clock implementation",
        "Date": "Fri,  1 Sep 2017 16:53:43 +0200",
        "Message-Id": "<20170901145343.19890-4-thierry.reding@gmail.com>",
        "X-Mailer": "git-send-email 2.13.3",
        "In-Reply-To": "<20170901145343.19890-1-thierry.reding@gmail.com>",
        "References": "<20170901145343.19890-1-thierry.reding@gmail.com>",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "From: Thierry Reding <treding@nvidia.com>\n\nThis clock was previously called sor1_src and was modelled as an input\nto the sor1 module clock. However, it's really an output clock that can\nbe fed either from the safe, the sor1_pad_clkout or the sor1 module\nclocks. sor1 itself can take input from either of the display PLLs.\n\nThe same implementation for the sor1_out clock is used on Tegra186, so\nthis nicely lines up both SoC generations to deal with this clock in a\nuniform way.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/clk/tegra/clk-tegra-periph.c | 16 ------------\n drivers/clk/tegra/clk-tegra210.c     | 47 ++++++++++++++++++++++++++++++++++++\n 2 files changed, 47 insertions(+), 16 deletions(-)",
    "diff": "diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\nindex 090a5d792341..c7694205573f 100644\n--- a/drivers/clk/tegra/clk-tegra-periph.c\n+++ b/drivers/clk/tegra/clk-tegra-periph.c\n@@ -129,7 +129,6 @@\n #define CLK_SOURCE_NVDEC 0x698\n #define CLK_SOURCE_NVJPG 0x69c\n #define CLK_SOURCE_APE 0x6c0\n-#define CLK_SOURCE_SOR1 0x410\n #define CLK_SOURCE_SDMMC_LEGACY 0x694\n #define CLK_SOURCE_QSPI 0x6c4\n #define CLK_SOURCE_VI_I2C 0x6c8\n@@ -278,7 +277,6 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);\n static DEFINE_SPINLOCK(PLLP_OUTB_lock);\n static DEFINE_SPINLOCK(PLLP_OUTC_lock);\n static DEFINE_SPINLOCK(sor0_lock);\n-static DEFINE_SPINLOCK(sor1_lock);\n \n #define MUX_I2S_SPDIF(_id)\t\t\t\t\t\t\\\n static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \"pll_a_out0\", \\\n@@ -604,18 +602,6 @@ static u32 mux_pllp_plld_plld2_clkm_idx[] = {\n \t[0] = 0, [1] = 2, [2] = 5, [3] = 6\n };\n \n-static const char *mux_sor_safe_sor1_brick_sor1_src[] = {\n-\t/*\n-\t * Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the\n-\t * sor1_brick parent appears twice in the list below. This is merely\n-\t * to support clk_get_parent() if firmware happened to set these bits\n-\t * to 0b11. While not an invalid setting, code should always set the\n-\t * bits to 0b01 to select sor1_brick.\n-\t */\n-\t\"sor_safe\", \"sor1_brick\", \"sor1_src\", \"sor1_brick\"\n-};\n-#define mux_sor_safe_sor1_brick_sor1_src_idx NULL\n-\n static const char *mux_pllp_pllre_clkm[] = {\n \t\"pll_p\", \"pll_re_out1\", \"clk_m\"\n };\n@@ -804,8 +790,6 @@ static struct tegra_periph_init_data periph_clks[] = {\n \tMUX8(\"nvdec\", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),\n \tMUX8(\"nvjpg\", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),\n \tMUX8(\"ape\", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),\n-\tMUX8_NOGATE_LOCK(\"sor1_src\", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),\n-\tNODIV(\"sor1\", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),\n \tMUX8(\"sdmmc_legacy\", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),\n \tMUX8(\"qspi\", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),\n \tI2C(\"vii2c\", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),\ndiff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c\nindex 6d7a613f2656..be7b736371f6 100644\n--- a/drivers/clk/tegra/clk-tegra210.c\n+++ b/drivers/clk/tegra/clk-tegra210.c\n@@ -40,6 +40,7 @@\n \n #define CLK_SOURCE_CSITE 0x1d4\n #define CLK_SOURCE_EMC 0x19c\n+#define CLK_SOURCE_SOR1 0x410\n \n #define PLLC_BASE 0x80\n #define PLLC_OUT 0x84\n@@ -264,6 +265,7 @@ static DEFINE_SPINLOCK(pll_d_lock);\n static DEFINE_SPINLOCK(pll_e_lock);\n static DEFINE_SPINLOCK(pll_re_lock);\n static DEFINE_SPINLOCK(pll_u_lock);\n+static DEFINE_SPINLOCK(sor1_lock);\n static DEFINE_SPINLOCK(emc_lock);\n \n /* possible OSC frequencies in Hz */\n@@ -2628,10 +2630,35 @@ static int tegra210_init_pllu(void)\n \treturn 0;\n }\n \n+static const char * const sor1_out_parents[] = {\n+\t/*\n+\t * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so\n+\t * the sor1_pad_clkout parent appears twice in the list below. This is\n+\t * merely to support clk_get_parent() if firmware happened to set\n+\t * these bits to 0b11. While not an invalid setting, code should\n+\t * always set the bits to 0b01 to select sor1_pad_clkout.\n+\t */\n+\t\"sor_safe\", \"sor1_pad_clkout\", \"sor1\", \"sor1_pad_clkout\",\n+};\n+\n+static const char * const sor1_parents[] = {\n+\t\"pll_p\", \"pll_d_out0\", \"pll_d2_out0\", \"clk_m\",\n+};\n+\n+static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };\n+\n+static struct tegra_periph_init_data tegra210_periph[] = {\n+\tTEGRA_INIT_DATA_TABLE(\"sor1\", NULL, NULL, sor1_parents,\n+\t\t\t      CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,\n+\t\t\t      TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,\n+\t\t\t      sor1_parents_idx, 0, &sor1_lock),\n+};\n+\n static __init void tegra210_periph_clk_init(void __iomem *clk_base,\n \t\t\t\t\t    void __iomem *pmc_base)\n {\n \tstruct clk *clk;\n+\tunsigned int i;\n \n \t/* xusb_ss_div2 */\n \tclk = clk_register_fixed_factor(NULL, \"xusb_ss_div2\", \"xusb_ss_src\", 0,\n@@ -2650,6 +2677,12 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,\n \t\t\t\t\t      1, 17, 207);\n \tclks[TEGRA210_CLK_DPAUX1] = clk;\n \n+\tclk = clk_register_mux_table(NULL, \"sor1_out\", sor1_out_parents,\n+\t\t\t\t     ARRAY_SIZE(sor1_out_parents), 0,\n+\t\t\t\t     clk_base + CLK_SOURCE_SOR1, 14, 0x3,\n+\t\t\t\t     0, NULL, &sor1_lock);\n+\tclks[TEGRA210_CLK_SOR1_OUT] = clk;\n+\n \t/* pll_d_dsi_out */\n \tclk = clk_register_gate(NULL, \"pll_d_dsi_out\", \"pll_d_out0\", 0,\n \t\t\t\tclk_base + PLLD_MISC0, 21, 0, &pll_d_lock);\n@@ -2694,6 +2727,20 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,\n \t\t\t\t0, NULL);\n \tclks[TEGRA210_CLK_ACLK] = clk;\n \n+\tfor (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {\n+\t\tstruct tegra_periph_init_data *init = &tegra210_periph[i];\n+\t\tstruct clk **clkp;\n+\n+\t\tclkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);\n+\t\tif (!clkp) {\n+\t\t\tpr_warn(\"clock %u not found\\n\", init->clk_id);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tclk = tegra_clk_register_periph_data(clk_base, init);\n+\t\t*clkp = clk;\n+\t}\n+\n \ttegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);\n }\n \n",
    "prefixes": [
        "4/4"
    ]
}