[{"id":1797719,"web_url":"http://patchwork.ozlabs.org/comment/1797719/","msgid":"<20171102081656.GM11011@codeaurora.org>","list_archive_url":null,"date":"2017-11-02T08:16:56","subject":"Re: [PATCH 4/4] clk: tegra: Fix sor1_out clock implementation","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/01, Thierry Reding wrote:\n> From: Thierry Reding <treding@nvidia.com>\n> \n> This clock was previously called sor1_src and was modelled as an input\n> to the sor1 module clock. However, it's really an output clock that can\n> be fed either from the safe, the sor1_pad_clkout or the sor1 module\n> clocks. sor1 itself can take input from either of the display PLLs.\n> \n> The same implementation for the sor1_out clock is used on Tegra186, so\n> this nicely lines up both SoC generations to deal with this clock in a\n> uniform way.\n> \n> Signed-off-by: Thierry Reding <treding@nvidia.com>\n> ---\n\nApplied to clk-next","headers":{"Return-Path":"<linux-tegra-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"cEgWfy9i\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"X3661KjC\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySHxR6RQxz9t2f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu,  2 Nov 2017 19:16:59 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751567AbdKBIQ7 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 2 Nov 2017 04:16:59 -0400","from smtp.codeaurora.org ([198.145.29.96]:41314 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755191AbdKBIQ5 (ORCPT\n\t<rfc822; linux-tegra@vger.kernel.org>); Thu, 2 Nov 2017 04:16:57 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 892F8607EA; Thu,  2 Nov 2017 08:16:57 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id A4C02607BD;\n\tThu,  2 Nov 2017 08:16:56 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1509610617;\n\tbh=mxV3ZJOOWnWvY2vAFcps7z1+L7zwPN6QIIm8o6uxBPw=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=cEgWfy9ijThVqmhSq2C6hyiimdhnd1R8s8t6AVQ6unwwuxIHdXTsSaD2UR34zh8Yj\n\tDrO21Pw3OYJUGHyvH1mlgCqwoxFW9jjMKLGP/XxUcIsOD+11ExfcMBUIvBKz1XfKKb\n\t4+Yy8R0FBhsXCxNoJLxS2UcmDhMvV2WRgk3rcnIE=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1509610616;\n\tbh=mxV3ZJOOWnWvY2vAFcps7z1+L7zwPN6QIIm8o6uxBPw=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=X3661KjCYO0PV9qX98R+DTW4n6nUrQArbybZMrNvumYXi5VBa6Xb7y6cW3+fsAsf6\n\toWtusdKwKwyelOr1HGajSBDMaJNKCsPFFhl93ST0PhXRW3LxHdqgSI1ULfHguslfsn\n\t6Iu09E7SmxD1+fEzSNxzQ9pTzMRkwHxgjbzmPYhI="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org A4C02607BD","Date":"Thu, 2 Nov 2017 01:16:56 -0700","From":"Stephen Boyd <sboyd@codeaurora.org>","To":"Thierry Reding <thierry.reding@gmail.com>","Cc":"Michael Turquette <mturquette@baylibre.com>,\n\tPeter De Schrijver <pdeschrijver@nvidia.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tlinux-clk@vger.kernel.org, linux-tegra@vger.kernel.org","Subject":"Re: [PATCH 4/4] clk: tegra: Fix sor1_out clock implementation","Message-ID":"<20171102081656.GM11011@codeaurora.org>","References":"<20170901145343.19890-1-thierry.reding@gmail.com>\n\t<20170901145343.19890-4-thierry.reding@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170901145343.19890-4-thierry.reding@gmail.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-tegra.vger.kernel.org>","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]