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GET /api/patches/807325/?format=api
{ "id": 807325, "url": "http://patchwork.ozlabs.org/api/patches/807325/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/75124dce-5afd-12bf-26a9-3370904c869f@linux.vnet.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<75124dce-5afd-12bf-26a9-3370904c869f@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-08-29T21:47:18", "name": "[v2,rs6000] Fix PR81833", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9410d901530f3ff2929fa0f13faf19293b4a61f2", "submitter": { "id": 6459, "url": "http://patchwork.ozlabs.org/api/people/6459/?format=api", "name": "Bill Schmidt", "email": "wschmidt@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/75124dce-5afd-12bf-26a9-3370904c869f@linux.vnet.ibm.com/mbox/", "series": [ { "id": 487, "url": "http://patchwork.ozlabs.org/api/series/487/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=487", "date": "2017-08-29T21:47:18", "name": "[v2,rs6000] Fix PR81833", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/487/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807325/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461124-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461124-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"IIwpzl+X\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhj0p3bqzz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 07:47:36 +1000 (AEST)", "(qmail 92234 invoked by alias); 29 Aug 2017 21:47:28 -0000", "(qmail 92225 invoked by uid 89); 29 Aug 2017 21:47:27 -0000", "from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.156.1) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 29 Aug 2017 21:47:25 +0000", "from pps.filterd (m0098404.ppops.net [127.0.0.1])\tby\n\tmx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7TLkFU9147163\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 29 Aug 2017 17:47:23 -0400", "from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208])\tby\n\tmx0a-001b2d01.pphosted.com with ESMTP id\n\t2cna46jtjw-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 29 Aug 2017 17:47:23 -0400", "from localhost\tby e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted\tfor\n\t<gcc-patches@gcc.gnu.org> from <wschmidt@linux.vnet.ibm.com>;\n\tTue, 29 Aug 2017 17:47:21 -0400", "from b01cxnp22035.gho.pok.ibm.com (9.57.198.25)\tby\n\te18.ny.us.ibm.com (146.89.104.205) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted;\n\tTue, 29 Aug 2017 17:47:20 -0400", "from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com\n\t[9.57.199.109])\tby b01cxnp22035.gho.pok.ibm.com\n\t(8.14.9/8.14.9/NCO v10.0) with ESMTP id v7TLlJjP32833570;\n\tTue, 29 Aug 2017 21:47:19 GMT", "from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1])\tby IMSVA\n\t(Postfix) with ESMTP id E9E59112054;\n\tTue, 29 Aug 2017 17:47:05 -0400 (EDT)", "from BigMac.local (unknown [9.80.238.20])\tby\n\tb01ledav004.gho.pok.ibm.com (Postfix) with ESMTP id\n\t9690A112047; Tue, 29 Aug 2017 17:47:05 -0400 (EDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:to:cc\n\t:from:subject:date:mime-version:content-type\n\t:content-transfer-encoding:message-id; q=dns; s=default; b=Odq3F\n\tOeVbHLOSkeHO4wfF7p4OjQvto4diTNXF1JvtxuShm9DrYjDUKKUdjp7jLEL8RgMb\n\tkk1Z3cx+do1CZh2ZloIJBetjFEdwC+exdE+i6BQTflY0HAWsiZqHSlOytUmaZnbi\n\tZm7TnXecRhh5ak6CR2QJCin4fTlSKL2d4neks4=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:to:cc\n\t:from:subject:date:mime-version:content-type\n\t:content-transfer-encoding:message-id; s=default; bh=9FI4zd7JKvS\n\tYcZOAyaEx9NCTKYE=; b=IIwpzl+XcZuxUCXk0NGnaza6E9Gtg6hGB7fwLxND6QL\n\tbX087AjC9+lcL9WhCWorLHcK/hCvLAuIiPvT2MuI99lIqC16ixzwq6fZQzWVK3/U\n\tTutv5Gk/7n6vbuF8P1MoExzvaoCM/RUMMq71nDazocqaBsGY0bGCLIS3Y+RRFS/8\n\t=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-10.2 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=", "X-HELO": "mx0a-001b2d01.pphosted.com", "To": "GCC Patches <gcc-patches@gcc.gnu.org>", "Cc": "Segher Boessenkool <segher@kernel.crashing.org>,\n\tDavid Edelsohn <dje.gcc@gmail.com>", "From": "Bill Schmidt <wschmidt@linux.vnet.ibm.com>", "Subject": "[PATCH v2, rs6000] Fix PR81833", "Date": "Tue, 29 Aug 2017 16:47:18 -0500", "User-Agent": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12;\n\trv:52.0) Gecko/20100101 Thunderbird/52.3.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=utf-8", "Content-Transfer-Encoding": "7bit", "X-TM-AS-GCONF": "00", "x-cbid": "17082921-0044-0000-0000-00000384E6BD", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007633; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909425; UDB=6.00456107;\n\tIPR=6.00689709; BA=6.00005560; NDR=6.00000001; ZLA=6.00000005;\n\tZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000;\n\tZU=6.00000002; MB=3.00016921; XFM=3.00000015;\n\tUTC=2017-08-29 21:47:21", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082921-0045-0000-0000-000007B2FF3C", "Message-Id": "<75124dce-5afd-12bf-26a9-3370904c869f@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_09:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0 malwarescore=0 phishscore=0\n\tadultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290330", "X-IsSubscribed": "yes" }, "content": "Hi Segher,\n\nThanks for approving the previous patch with changes. I've made those and also\nmodified the test case to require VSX hardware for execution. I duplicated the\ntest so we get coverage on P7 BE 32/64 and P8 BE/LE. I'd appreciate it if you\ncould look over the dejagnu instructions once more on these. Thanks!\n\nBill\n\n\n[gcc]\n\n2017-08-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>\n\n\tPR target/81833\n\t* config/rs6000/altivec.md (altivec_vsum2sws): Convert from a\n\tdefine_insn to a define_expand.\n\t(altivec_vsum2sws_direct): New define_insn.\n\t(altivec_vsumsws): Convert from a define_insn to a define_expand.\n\n[gcc/testsuite]\n\n2017-08-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>\n\n\tPR target/81833\n\t* gcc.target/powerpc/pr81833-1.c: New file.\n\t* gcc.target/powerpc/pr81833-2.c: New file.", "diff": "Index: gcc/config/rs6000/altivec.md\n===================================================================\n--- gcc/config/rs6000/altivec.md\t(revision 251369)\n+++ gcc/config/rs6000/altivec.md\t(working copy)\n@@ -1804,51 +1804,61 @@\n \"vsum4s<VI_char>s %0,%1,%2\"\n [(set_attr \"type\" \"veccomplex\")])\n \n-;; FIXME: For the following two patterns, the scratch should only be\n-;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should\n-;; be emitted separately.\n-(define_insn \"altivec_vsum2sws\"\n- [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n- (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n- (match_operand:V4SI 2 \"register_operand\" \"v\")]\n-\t\t UNSPEC_VSUM2SWS))\n- (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))\n- (clobber (match_scratch:V4SI 3 \"=v\"))]\n+(define_expand \"altivec_vsum2sws\"\n+ [(use (match_operand:V4SI 0 \"register_operand\"))\n+ (use (match_operand:V4SI 1 \"register_operand\"))\n+ (use (match_operand:V4SI 2 \"register_operand\"))]\n \"TARGET_ALTIVEC\"\n {\n if (VECTOR_ELT_ORDER_BIG)\n- return \"vsum2sws %0,%1,%2\";\n+ emit_insn (gen_altivec_vsum2sws_direct (operands[0], operands[1],\n+ operands[2]));\n else\n- return \"vsldoi %3,%2,%2,12\\n\\tvsum2sws %3,%1,%3\\n\\tvsldoi %0,%3,%3,4\";\n-}\n- [(set_attr \"type\" \"veccomplex\")\n- (set (attr \"length\")\n- (if_then_else\n- (match_test \"VECTOR_ELT_ORDER_BIG\")\n- (const_string \"4\")\n- (const_string \"12\")))])\n+ {\n+ rtx tmp1 = gen_reg_rtx (V4SImode);\n+ rtx tmp2 = gen_reg_rtx (V4SImode);\n+ emit_insn (gen_altivec_vsldoi_v4si (tmp1, operands[2],\n+ operands[2], GEN_INT (12)));\n+ emit_insn (gen_altivec_vsum2sws_direct (tmp2, operands[1], tmp1));\n+ emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,\n+ GEN_INT (4)));\n+ }\n+ DONE;\n+})\n \n-(define_insn \"altivec_vsumsws\"\n+; FIXME: This can probably be expressed without an UNSPEC.\n+(define_insn \"altivec_vsum2sws_direct\"\n [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\n- (match_operand:V4SI 2 \"register_operand\" \"v\")]\n-\t\t UNSPEC_VSUMSWS))\n- (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))\n- (clobber (match_scratch:V4SI 3 \"=v\"))]\n+\t (match_operand:V4SI 2 \"register_operand\" \"v\")]\n+\t\t UNSPEC_VSUM2SWS))\n+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]\n \"TARGET_ALTIVEC\"\n+ \"vsum2sws %0,%1,%2\"\n+ [(set_attr \"type\" \"veccomplex\")])\n+\n+(define_expand \"altivec_vsumsws\"\n+ [(use (match_operand:V4SI 0 \"register_operand\"))\n+ (use (match_operand:V4SI 1 \"register_operand\"))\n+ (use (match_operand:V4SI 2 \"register_operand\"))]\n+ \"TARGET_ALTIVEC\"\n {\n if (VECTOR_ELT_ORDER_BIG)\n- return \"vsumsws %0,%1,%2\";\n+ emit_insn (gen_altivec_vsumsws_direct (operands[0], operands[1],\n+ operands[2]));\n else\n- return \"vspltw %3,%2,0\\n\\tvsumsws %3,%1,%3\\n\\tvsldoi %0,%3,%3,12\";\n-}\n- [(set_attr \"type\" \"veccomplex\")\n- (set (attr \"length\")\n- (if_then_else\n- (match_test \"(VECTOR_ELT_ORDER_BIG)\")\n- (const_string \"4\")\n- (const_string \"12\")))])\n+ {\n+ rtx tmp1 = gen_reg_rtx (V4SImode);\n+ rtx tmp2 = gen_reg_rtx (V4SImode);\n+ emit_insn (gen_altivec_vspltw_direct (tmp1, operands[2], const0_rtx));\n+ emit_insn (gen_altivec_vsumsws_direct (tmp2, operands[1], tmp1));\n+ emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,\n+ GEN_INT (12)));\n+ }\n+ DONE;\n+})\n \n+; FIXME: This can probably be expressed without an UNSPEC.\n (define_insn \"altivec_vsumsws_direct\"\n [(set (match_operand:V4SI 0 \"register_operand\" \"=v\")\n (unspec:V4SI [(match_operand:V4SI 1 \"register_operand\" \"v\")\nIndex: gcc/testsuite/gcc.target/powerpc/pr81833-1.c\n===================================================================\n--- gcc/testsuite/gcc.target/powerpc/pr81833-1.c\t(nonexistent)\n+++ gcc/testsuite/gcc.target/powerpc/pr81833-1.c\t(working copy)\n@@ -0,0 +1,59 @@\n+/* PR81833: This used to fail due to improper implementation of vec_msum. */\n+/* Test case relies on -mcpu=power7 or later. Currently we don't have\n+ machinery to express that, so we have two separate tests for -mcpu=power7\n+ and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8. */\n+\n+/* { dg-do run } */\n+/* { dg-require-effective-target vsx_hw } */\n+/* { dg-skip-if \"do not override -mcpu\" { powerpc*-*-* } { \"-mcpu=*\" } { \"-mcpu=power8\" } } */\n+/* { dg-options \"-mcpu=power8 -O2\" } */\n+\n+#include <altivec.h>\n+\n+#define vec_u8 vector unsigned char\n+#define vec_s8 vector signed char\n+#define vec_u16 vector unsigned short\n+#define vec_s16 vector signed short\n+#define vec_u32 vector unsigned int\n+#define vec_s32 vector signed int\n+#define vec_f vector float\n+\n+#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)\n+\n+#define zero_u8v (vec_u8) zerov\n+#define zero_s8v (vec_s8) zerov\n+#define zero_u16v (vec_u16) zerov\n+#define zero_s16v (vec_s16) zerov\n+#define zero_u32v (vec_u32) zerov\n+#define zero_s32v (vec_s32) zerov\n+\n+signed int __attribute__((noinline))\n+scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,\n+\t\t\t int order)\n+{\n+ int i;\n+ LOAD_ZERO;\n+ register vec_s16 vec1;\n+ register vec_s32 res = vec_splat_s32 (0), t;\n+ signed int ires;\n+\n+ for (i = 0; i < order; i += 8) {\n+ vec1 = vec_vsx_ld (0, v1);\n+ t = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);\n+ res = vec_sums (t, res);\n+ v1 += 8;\n+ v2 += 8;\n+ }\n+ res = vec_splat (res, 3);\n+ vec_ste (res, 0, &ires);\n+\n+ return ires;\n+}\n+\n+int main(void)\n+{\n+ const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };\n+ if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)\n+ __builtin_abort ();\n+ return 0;\n+}\nIndex: gcc/testsuite/gcc.target/powerpc/pr81833-2.c\n===================================================================\n--- gcc/testsuite/gcc.target/powerpc/pr81833-2.c\t(nonexistent)\n+++ gcc/testsuite/gcc.target/powerpc/pr81833-2.c\t(working copy)\n@@ -0,0 +1,59 @@\n+/* PR81833: This used to fail due to improper implementation of vec_msum. */\n+/* Test case relies on -mcpu=power7 or later. Currently we don't have\n+ machinery to express that, so we have two separate tests for -mcpu=power7\n+ and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8. */\n+\n+/* { dg-do run } */\n+/* { dg-require-effective-target vsx_hw } */\n+/* { dg-skip-if \"do not override -mcpu\" { powerpc*-*-* } { \"-mcpu=*\" } { \"-mcpu=power7\" } } */\n+/* { dg-options \"-mcpu=power7 -O2\" } */\n+\n+#include <altivec.h>\n+\n+#define vec_u8 vector unsigned char\n+#define vec_s8 vector signed char\n+#define vec_u16 vector unsigned short\n+#define vec_s16 vector signed short\n+#define vec_u32 vector unsigned int\n+#define vec_s32 vector signed int\n+#define vec_f vector float\n+\n+#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)\n+\n+#define zero_u8v (vec_u8) zerov\n+#define zero_s8v (vec_s8) zerov\n+#define zero_u16v (vec_u16) zerov\n+#define zero_s16v (vec_s16) zerov\n+#define zero_u32v (vec_u32) zerov\n+#define zero_s32v (vec_s32) zerov\n+\n+signed int __attribute__((noinline))\n+scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,\n+\t\t\t int order)\n+{\n+ int i;\n+ LOAD_ZERO;\n+ register vec_s16 vec1;\n+ register vec_s32 res = vec_splat_s32 (0), t;\n+ signed int ires;\n+\n+ for (i = 0; i < order; i += 8) {\n+ vec1 = vec_vsx_ld (0, v1);\n+ t = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);\n+ res = vec_sums (t, res);\n+ v1 += 8;\n+ v2 += 8;\n+ }\n+ res = vec_splat (res, 3);\n+ vec_ste (res, 0, &ires);\n+\n+ return ires;\n+}\n+\n+int main(void)\n+{\n+ const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };\n+ if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)\n+ __builtin_abort ();\n+ return 0;\n+}\n", "prefixes": [ "v2", "rs6000" ] }