Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/805828/?format=api
{ "id": 805828, "url": "http://patchwork.ozlabs.org/api/patches/805828/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503658973-14818-1-git-send-email-sbabic@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503658973-14818-1-git-send-email-sbabic@denx.de>", "list_archive_url": null, "date": "2017-08-25T11:02:53", "name": "[U-Boot] pfla02: Fix RAM detection and support 1 bank SOM", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "04ec3f9015106dc484cfc6eacff7576255796b75", "submitter": { "id": 5771, "url": "http://patchwork.ozlabs.org/api/people/5771/?format=api", "name": "Stefano Babic", "email": "sbabic@denx.de" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503658973-14818-1-git-send-email-sbabic@denx.de/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805828/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805828/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdyv55y3mz9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 25 Aug 2017 21:03:12 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 19EC9C21E60; Fri, 25 Aug 2017 11:03:07 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C3843C21E60;\n\tFri, 25 Aug 2017 11:03:04 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B4C39C21E60; Fri, 25 Aug 2017 11:03:03 +0000 (UTC)", "from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id 6B35DC21D78\n\tfor <u-boot@lists.denx.de>; Fri, 25 Aug 2017 11:03:03 +0000 (UTC)", "from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3xdytv1gT3z1rCxc;\n\tFri, 25 Aug 2017 13:03:03 +0200 (CEST)", "from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3xdytv1GgWz3hhTP;\n\tFri, 25 Aug 2017 13:03:03 +0200 (CEST)", "from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id EH8G8xpDKVc8; Fri, 25 Aug 2017 13:03:02 +0200 (CEST)", "from babic.homelinux.org (host-88-217-136-221.customer.m-online.net\n\t[88.217.136.221])\n\t(using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPS;\n\tFri, 25 Aug 2017 13:03:02 +0200 (CEST)", "from localhost (mail.babic.homelinux.org [127.0.0.1])\n\tby babic.homelinux.org (Postfix) with ESMTP id EFC494540458;\n\tFri, 25 Aug 2017 13:03:01 +0200 (CEST)", "from babic.homelinux.org ([127.0.0.1])\n\tby localhost (mail.babic.homelinux.org [127.0.0.1]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id iw-jQym9i5su; Fri, 25 Aug 2017 13:02:55 +0200 (CEST)", "from papero.fritz.box (papero.fritz.box [192.168.178.132])\n\tby babic.homelinux.org (Postfix) with ESMTP id 99FA9454019C;\n\tFri, 25 Aug 2017 13:02:55 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "X-Virus-Scanned": [ "amavisd-new at mnet-online.de", "Debian amavisd-new at babic.homelinux.org" ], "From": "Stefano Babic <sbabic@denx.de>", "To": "u-boot@lists.denx.de", "Date": "Fri, 25 Aug 2017 13:02:53 +0200", "Message-Id": "<1503658973-14818-1-git-send-email-sbabic@denx.de>", "X-Mailer": "git-send-email 2.7.4", "Subject": "[U-Boot] [PATCH] pfla02: Fix RAM detection and support 1 bank SOM", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "In case of 2 banks, the address space of the first CS must be defined\nand not let to the higher value.\n\nAdd support for SOM with a single bank of RAM. It was tested with i.MX6Q\nmodules in the following configurations:\n\n- 2 Banks, 4 GB\n- 2 Banks, 1 GB\n- 1 Bank, 1 GB\n\nSigned-off-by: Stefano Babic <sbabic@denx.de>\n---\n board/phytec/pfla02/Kconfig | 6 +++\n board/phytec/pfla02/pfla02.c | 87 +++++++++++++++++++++++++++-----------------\n 2 files changed, 60 insertions(+), 33 deletions(-)", "diff": "diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig\nindex 142a122..f4da68b 100644\n--- a/board/phytec/pfla02/Kconfig\n+++ b/board/phytec/pfla02/Kconfig\n@@ -9,4 +9,10 @@ config SYS_VENDOR\n config SYS_CONFIG_NAME\n \tdefault \"pfla02\"\n \n+config SPL_DRAM_1_BANK\n+\tbool \"DRAM on just one bank\"\n+\thelp\n+\t activate, if the module has just one bank\n+\t of RAM\n+\n endif\ndiff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c\nindex 8d2ce63..10b63e9 100644\n--- a/board/phytec/pfla02/pfla02.c\n+++ b/board/phytec/pfla02/pfla02.c\n@@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = {\n \n /* Index in RAM Chip array */\n enum {\n-\tRAM_1GB,\n-\tRAM_2GB,\n-\tRAM_4GB\n+\tRAM_MT64K,\n+\tRAM_MT128K,\n+\tRAM_MT256K\n };\n \n static struct mx6_ddr3_cfg mt41k_xx[] = {\n@@ -561,31 +561,11 @@ static void gpr_init(void)\n \twritel(0x007F007F, &iomux->gpr[7]);\n }\n \n-static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)\n+static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,\n+\t\t\t\tstruct mx6_ddr3_cfg *mem_ddr)\n {\n-\tstruct mx6_ddr_sysinfo sysinfo = {\n-\t\t/* width of data bus:0=16,1=32,2=64 */\n-\t\t.dsize = 2,\n-\t\t/* config for full 4GB range so that get_mem_size() works */\n-\t\t.cs_density = 32, /* 32Gb per CS */\n-\t\t/* single chip select */\n-\t\t.ncs = 2,\n-\t\t.cs1_mirror = 0,\n-\t\t.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,\t/* RTT_Wr = RZQ/4 */\n-\t\t.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,\t/* RTT_Nom = RZQ/4 */\n-\t\t.walat = 1,\t/* Write additional latency */\n-\t\t.ralat = 5,\t/* Read additional latency */\n-\t\t.mif3_mode = 3,\t/* Command prediction working mode */\n-\t\t.bi_on = 1,\t/* Bank interleaving enabled */\n-\t\t.sde_to_rst = 0x10,\t/* 14 cycles, 200us (JEDEC default) */\n-\t\t.rst_to_cke = 0x23,\t/* 33 cycles, 500us (JEDEC default) */\n-\t\t.ddr_type = DDR_TYPE_DDR3,\n-\t\t.refsel = 1,\t/* Refresh cycles at 32KHz */\n-\t\t.refr = 7,\t/* 8 refresh commands per refresh cycle */\n-\t};\n-\n \tmx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);\n-\tmx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr);\n+\tmx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);\n }\n \n int board_mmc_init(bd_t *bis)\n@@ -627,10 +607,12 @@ void board_boot_order(u32 *spl_boot_list)\n * Function checks for mirrors in the first CS\n */\n #define RAM_TEST_PATTERN\t0xaa5555aa\n-static unsigned int pfla02_detect_ramsize(void)\n+#define MIN_BANK_SIZE\t\t(512 * 1024 * 1024)\n+\n+static unsigned int pfla02_detect_chiptype(void)\n {\n \tu32 *p, *p1;\n-\tunsigned int offset = 512 * 1024 * 1024;\n+\tunsigned int offset = MIN_BANK_SIZE;\n \tint i;\n \n \tfor (i = 0; i < 2; i++) {\n@@ -649,12 +631,38 @@ static unsigned int pfla02_detect_ramsize(void)\n \t\tif (*p == *p1)\n \t\t\treturn i;\n \t}\n-\treturn RAM_4GB;\n+\treturn RAM_MT256K;\n }\n \n void board_init_f(ulong dummy)\n {\n \tunsigned int ramchip;\n+\n+\tstruct mx6_ddr_sysinfo sysinfo = {\n+\t\t/* width of data bus:0=16,1=32,2=64 */\n+\t\t.dsize = 2,\n+\t\t/* config for full 4GB range so that get_mem_size() works */\n+\t\t.cs_density = 32, /* 512 MB */\n+\t\t/* single chip select */\n+#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)\n+\t\t.ncs = 1,\n+#else\n+\t\t.ncs = 2,\n+#endif\n+\t\t.cs1_mirror = 1,\n+\t\t.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,\t/* RTT_Wr = RZQ/4 */\n+\t\t.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,\t/* RTT_Nom = RZQ/4 */\n+\t\t.walat = 1,\t/* Write additional latency */\n+\t\t.ralat = 5,\t/* Read additional latency */\n+\t\t.mif3_mode = 3,\t/* Command prediction working mode */\n+\t\t.bi_on = 1,\t/* Bank interleaving enabled */\n+\t\t.sde_to_rst = 0x10,\t/* 14 cycles, 200us (JEDEC default) */\n+\t\t.rst_to_cke = 0x23,\t/* 33 cycles, 500us (JEDEC default) */\n+\t\t.ddr_type = DDR_TYPE_DDR3,\n+\t\t.refsel = 1,\t/* Refresh cycles at 32KHz */\n+\t\t.refr = 7,\t/* 8 refresh commands per refresh cycle */\n+\t};\n+\n #ifdef CONFIG_CMD_NAND\n \t/* Enable NAND */\n \tsetup_gpmi_nand();\n@@ -682,10 +690,23 @@ void board_init_f(ulong dummy)\n \tsetup_gpios();\n \n \t/* DDR initialization */\n-\tspl_dram_init(&mt41k_xx[RAM_4GB]);\n-\tramchip = pfla02_detect_ramsize();\n-\tif (ramchip != RAM_4GB)\n-\t\tspl_dram_init(&mt41k_xx[ramchip]);\n+\tspl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);\n+\tramchip = pfla02_detect_chiptype();\n+\tdebug(\"Detected chip %d\\n\", ramchip);\n+#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)\n+\tswitch (ramchip) {\n+\t\tcase RAM_MT64K:\n+\t\t\tsysinfo.cs_density = 6;\n+\t\t\tbreak;\n+\t\tcase RAM_MT128K:\n+\t\t\tsysinfo.cs_density = 10;\n+\t\t\tbreak;\n+\t\tcase RAM_MT256K:\n+\t\t\tsysinfo.cs_density = 18;\n+\t\t\tbreak;\n+\t}\n+#endif\n+\tspl_dram_init(&sysinfo, &mt41k_xx[ramchip]);\n \n \t/* Clear the BSS. */\n \tmemset(__bss_start, 0, __bss_end - __bss_start);\n", "prefixes": [ "U-Boot" ] }