From patchwork Fri Aug 25 11:02:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Babic X-Patchwork-Id: 805828 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xdyv55y3mz9sRm for ; Fri, 25 Aug 2017 21:03:12 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 19EC9C21E60; Fri, 25 Aug 2017 11:03:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C3843C21E60; Fri, 25 Aug 2017 11:03:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B4C39C21E60; Fri, 25 Aug 2017 11:03:03 +0000 (UTC) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9]) by lists.denx.de (Postfix) with ESMTPS id 6B35DC21D78 for ; Fri, 25 Aug 2017 11:03:03 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 3xdytv1gT3z1rCxc; Fri, 25 Aug 2017 13:03:03 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 3xdytv1GgWz3hhTP; Fri, 25 Aug 2017 13:03:03 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id EH8G8xpDKVc8; Fri, 25 Aug 2017 13:03:02 +0200 (CEST) Received: from babic.homelinux.org (host-88-217-136-221.customer.m-online.net [88.217.136.221]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPS; Fri, 25 Aug 2017 13:03:02 +0200 (CEST) Received: from localhost (mail.babic.homelinux.org [127.0.0.1]) by babic.homelinux.org (Postfix) with ESMTP id EFC494540458; Fri, 25 Aug 2017 13:03:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at babic.homelinux.org Received: from babic.homelinux.org ([127.0.0.1]) by localhost (mail.babic.homelinux.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iw-jQym9i5su; Fri, 25 Aug 2017 13:02:55 +0200 (CEST) Received: from papero.fritz.box (papero.fritz.box [192.168.178.132]) by babic.homelinux.org (Postfix) with ESMTP id 99FA9454019C; Fri, 25 Aug 2017 13:02:55 +0200 (CEST) From: Stefano Babic To: u-boot@lists.denx.de Date: Fri, 25 Aug 2017 13:02:53 +0200 Message-Id: <1503658973-14818-1-git-send-email-sbabic@denx.de> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] pfla02: Fix RAM detection and support 1 bank SOM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In case of 2 banks, the address space of the first CS must be defined and not let to the higher value. Add support for SOM with a single bank of RAM. It was tested with i.MX6Q modules in the following configurations: - 2 Banks, 4 GB - 2 Banks, 1 GB - 1 Bank, 1 GB Signed-off-by: Stefano Babic --- board/phytec/pfla02/Kconfig | 6 +++ board/phytec/pfla02/pfla02.c | 87 +++++++++++++++++++++++++++----------------- 2 files changed, 60 insertions(+), 33 deletions(-) diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig index 142a122..f4da68b 100644 --- a/board/phytec/pfla02/Kconfig +++ b/board/phytec/pfla02/Kconfig @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pfla02" +config SPL_DRAM_1_BANK + bool "DRAM on just one bank" + help + activate, if the module has just one bank + of RAM + endif diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c index 8d2ce63..10b63e9 100644 --- a/board/phytec/pfla02/pfla02.c +++ b/board/phytec/pfla02/pfla02.c @@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = { /* Index in RAM Chip array */ enum { - RAM_1GB, - RAM_2GB, - RAM_4GB + RAM_MT64K, + RAM_MT128K, + RAM_MT256K }; static struct mx6_ddr3_cfg mt41k_xx[] = { @@ -561,31 +561,11 @@ static void gpr_init(void) writel(0x007F007F, &iomux->gpr[7]); } -static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr) +static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo, + struct mx6_ddr3_cfg *mem_ddr) { - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 2, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr); + mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr); } int board_mmc_init(bd_t *bis) @@ -627,10 +607,12 @@ void board_boot_order(u32 *spl_boot_list) * Function checks for mirrors in the first CS */ #define RAM_TEST_PATTERN 0xaa5555aa -static unsigned int pfla02_detect_ramsize(void) +#define MIN_BANK_SIZE (512 * 1024 * 1024) + +static unsigned int pfla02_detect_chiptype(void) { u32 *p, *p1; - unsigned int offset = 512 * 1024 * 1024; + unsigned int offset = MIN_BANK_SIZE; int i; for (i = 0; i < 2; i++) { @@ -649,12 +631,38 @@ static unsigned int pfla02_detect_ramsize(void) if (*p == *p1) return i; } - return RAM_4GB; + return RAM_MT256K; } void board_init_f(ulong dummy) { unsigned int ramchip; + + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 512 MB */ + /* single chip select */ +#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + .ncs = 1, +#else + .ncs = 2, +#endif + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); @@ -682,10 +690,23 @@ void board_init_f(ulong dummy) setup_gpios(); /* DDR initialization */ - spl_dram_init(&mt41k_xx[RAM_4GB]); - ramchip = pfla02_detect_ramsize(); - if (ramchip != RAM_4GB) - spl_dram_init(&mt41k_xx[ramchip]); + spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); + ramchip = pfla02_detect_chiptype(); + debug("Detected chip %d\n", ramchip); +#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + switch (ramchip) { + case RAM_MT64K: + sysinfo.cs_density = 6; + break; + case RAM_MT128K: + sysinfo.cs_density = 10; + break; + case RAM_MT256K: + sysinfo.cs_density = 18; + break; + } +#endif + spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);