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GET /api/patches/805475/?format=api
{ "id": 805475, "url": "http://patchwork.ozlabs.org/api/patches/805475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503579616-32426-1-git-send-email-breno.lima@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503579616-32426-1-git-send-email-breno.lima@nxp.com>", "list_archive_url": null, "date": "2017-08-24T13:00:16", "name": "[U-Boot] imx: imx6: Move gpr_init() function to soc.c", "commit_ref": "3aa4b703b483f165dd2eb5c3324b44b60fbb1672", "pull_url": null, "state": "accepted", "archived": false, "hash": "9dd99db41bfe159e7b3d20e8531df531377de413", "submitter": { "id": 69464, "url": "http://patchwork.ozlabs.org/api/people/69464/?format=api", "name": "Breno Matheus Lima", "email": "breno.lima@nxp.com" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503579616-32426-1-git-send-email-breno.lima@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805475/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "spf=fail (sender IP is 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id\n\tv7OCwgH3001086; Thu, 24 Aug 2017 05:58:43 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tKHOP_BIG_TO_CC, \n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Breno Lima <breno.lima@nxp.com>", "To": "<sbabic@denx.de>, <fabio.estevam@nxp.com>", "Date": "Thu, 24 Aug 2017 10:00:16 -0300", "Message-ID": "<1503579616-32426-1-git-send-email-breno.lima@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131480531287418234;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(13018025)(5005006)(13016025)(8121501046)(3002001)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6096035)(20161123556025)(20161123565025)(20161123561025)(20161123563025)(20161123559100)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY4PR03MB3318; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY4PR03MB3318; ", "X-Forefront-PRVS": "04097B7F7F", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Aug 2017 12:58:48.5390\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR03MB3318", "Cc": "marex@denx.de, albert.u.boot@aribaud.net, Breno Lima <breno.lima@nxp.com>,\n\tping.bai@nxp.com, otavio@ossystems.com.br, stefan.agner@toradex.com, \n\tu-boot@lists.denx.de, max.krummenacher@toradex.com, sr@denx.de", "Subject": "[U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,\nMX6Q and MX6QP processors move it to the soc.c file.\n\nSigned-off-by: Breno Lima <breno.lima@nxp.com>\n---\n arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++\n arch/arm/mach-imx/mx6/soc.c | 17 +++++++++++++++++\n board/bachmann/ot1200/ot1200.c | 11 -----------\n board/barco/platinum/platinum.h | 11 -----------\n board/congatec/cgtqmx6eval/cgtqmx6eval.c | 11 -----------\n board/el/el6x/el6x.c | 11 -----------\n board/engicam/common/spl.c | 11 -----------\n board/freescale/mx6sabreauto/mx6sabreauto.c | 17 -----------------\n board/freescale/mx6sabresd/mx6sabresd.c | 17 -----------------\n board/gateworks/gw_ventana/gw_ventana_spl.c | 11 -----------\n board/kosagi/novena/novena_spl.c | 11 -----------\n board/liebherr/mccmon6/spl.c | 11 -----------\n board/phytec/pcm058/pcm058.c | 12 ------------\n board/phytec/pfla02/pfla02.c | 11 -----------\n board/solidrun/mx6cuboxi/mx6cuboxi.c | 11 -----------\n board/toradex/apalis_imx6/apalis_imx6.c | 11 -----------\n board/toradex/colibri_imx6/colibri_imx6.c | 11 -----------\n board/udoo/udoo_spl.c | 11 -----------\n board/wandboard/spl.c | 11 -----------\n 19 files changed, 19 insertions(+), 200 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h\nindex 046df62..436ba9a 100644\n--- a/arch/arm/include/asm/mach-imx/sys_proto.h\n+++ b/arch/arm/include/asm/mach-imx/sys_proto.h\n@@ -85,6 +85,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)\n }\n \n u32 imx6_src_get_boot_mode(void);\n+void gpr_init(void);\n+\n #endif /* CONFIG_MX6 */\n \n u32 get_nr_cpus(void);\ndiff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c\nindex 9ede1f5..f8bc05e 100644\n--- a/arch/arm/mach-imx/mx6/soc.c\n+++ b/arch/arm/mach-imx/mx6/soc.c\n@@ -681,6 +681,23 @@ void imx_setup_hdmi(void)\n }\n #endif\n \n+void gpr_init(void)\n+{\n+\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n+\n+\t/* enable AXI cache for VDOA/VPU/IPU */\n+\twritel(0xF00000CF, &iomux->gpr[4]);\n+\tif (is_mx6dqp()) {\n+\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n+\t\twritel(0x77177717, &iomux->gpr[6]);\n+\t\twritel(0x77177717, &iomux->gpr[7]);\n+\t} else {\n+\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n+\t\twritel(0x007F007F, &iomux->gpr[6]);\n+\t\twritel(0x007F007F, &iomux->gpr[7]);\n+\t}\n+}\n+\n #ifdef CONFIG_IMX_BOOTAUX\n int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)\n {\ndiff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c\nindex df10d6a..9465cea 100644\n--- a/board/bachmann/ot1200/ot1200.c\n+++ b/board/bachmann/ot1200/ot1200.c\n@@ -169,17 +169,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n int board_early_init_f(void)\n {\n \tccgr_init();\ndiff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h\nindex d3ea8bd..3013ed9 100644\n--- a/board/barco/platinum/platinum.h\n+++ b/board/barco/platinum/platinum.h\n@@ -75,15 +75,4 @@ static inline void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static inline void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n #endif /* _PLATINUM_H_ */\ndiff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\nindex 8cd0090..2ed66d3 100644\n--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n@@ -955,17 +955,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n /* Define a minimal structure so that the part number can be read via SPL */\n struct mfgdata {\n \tunsigned char tsize;\ndiff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c\nindex 6b98b5c..fb128f5 100644\n--- a/board/el/el6x/el6x.c\n+++ b/board/el/el6x/el6x.c\n@@ -570,17 +570,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n /*\n * This section requires the differentiation between iMX6 Sabre boards, but\n * for now, it will configure only for the mx6q variant.\ndiff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c\nindex a8a7cf3..29a27ce 100644\n--- a/board/engicam/common/spl.c\n+++ b/board/engicam/common/spl.c\n@@ -332,17 +332,6 @@ static void ccgr_init(void)\n #endif\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(void)\n {\n #ifdef CONFIG_MX6QDL\ndiff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c\nindex f8f77f6..15ca029 100644\n--- a/board/freescale/mx6sabreauto/mx6sabreauto.c\n+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c\n@@ -798,23 +798,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\tif (is_mx6dqp()) {\n-\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n-\t\twritel(0x77177717, &iomux->gpr[6]);\n-\t\twritel(0x77177717, &iomux->gpr[7]);\n-\t} else {\n-\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\t\twritel(0x007F007F, &iomux->gpr[6]);\n-\t\twritel(0x007F007F, &iomux->gpr[7]);\n-\t}\n-}\n-\n static int mx6q_dcd_table[] = {\n \t0x020e0798, 0x000C0000,\n \t0x020e0758, 0x00000000,\ndiff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\nindex 9a562b3..5b50bc8 100644\n--- a/board/freescale/mx6sabresd/mx6sabresd.c\n+++ b/board/freescale/mx6sabresd/mx6sabresd.c\n@@ -747,23 +747,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\tif (is_mx6dqp()) {\n-\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n-\t\twritel(0x77177717, &iomux->gpr[6]);\n-\t\twritel(0x77177717, &iomux->gpr[7]);\n-\t} else {\n-\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\t\twritel(0x007F007F, &iomux->gpr[6]);\n-\t\twritel(0x007F007F, &iomux->gpr[7]);\n-\t}\n-}\n-\n static int mx6q_dcd_table[] = {\n \t0x020e0798, 0x000C0000,\n \t0x020e0758, 0x00000000,\ndiff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c\nindex 9524da7..c2e370b 100644\n--- a/board/gateworks/gw_ventana/gw_ventana_spl.c\n+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c\n@@ -583,17 +583,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n /*\n * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n * - we have a stack and a place to store GD, both in SRAM\ndiff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c\nindex 3645b75..512f06d 100644\n--- a/board/kosagi/novena/novena_spl.c\n+++ b/board/kosagi/novena/novena_spl.c\n@@ -550,17 +550,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n /*\n * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n * - we have a stack and a place to store GD, both in SRAM\ndiff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c\nindex 15844ef..a2f804d 100644\n--- a/board/liebherr/mccmon6/spl.c\n+++ b/board/liebherr/mccmon6/spl.c\n@@ -260,17 +260,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(void)\n {\n \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\ndiff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c\nindex 4257fbc..1538158 100644\n--- a/board/phytec/pcm058/pcm058.c\n+++ b/board/phytec/pcm058/pcm058.c\n@@ -487,18 +487,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n-\n static void spl_dram_init(void)\n {\n \tstruct mx6_ddr_sysinfo sysinfo = {\ndiff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c\nindex 8d2ce63..ec9264d 100644\n--- a/board/phytec/pfla02/pfla02.c\n+++ b/board/phytec/pfla02/pfla02.c\n@@ -550,17 +550,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)\n {\n \tstruct mx6_ddr_sysinfo sysinfo = {\ndiff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c\nindex 7e59fb2..986abc5 100644\n--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c\n+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c\n@@ -581,17 +581,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(int width)\n {\n \tstruct mx6_ddr_sysinfo sysinfo = {\ndiff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c\nindex 2fd9623..ebc6c12 100644\n--- a/board/toradex/apalis_imx6/apalis_imx6.c\n+++ b/board/toradex/apalis_imx6/apalis_imx6.c\n@@ -1160,17 +1160,6 @@ static void ccgr_init(void)\n \twritel(0x000000FB, &ccm->ccosr);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void ddr_init(int *table, int size)\n {\n \tint i;\ndiff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c\nindex d30391f..669d912 100644\n--- a/board/toradex/colibri_imx6/colibri_imx6.c\n+++ b/board/toradex/colibri_imx6/colibri_imx6.c\n@@ -1037,17 +1037,6 @@ static void ccgr_init(void)\n \twritel(0x000000FB, &ccm->ccosr);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void ddr_init(int *table, int size)\n {\n \tint i;\ndiff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c\nindex e83e7c3..3645969 100644\n--- a/board/udoo/udoo_spl.c\n+++ b/board/udoo/udoo_spl.c\n@@ -211,17 +211,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000FF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(void)\n {\n \tif (is_cpu_type(MXC_CPU_MX6DL)) {\ndiff --git a/board/wandboard/spl.c b/board/wandboard/spl.c\nindex 47082a8..99a0286 100644\n--- a/board/wandboard/spl.c\n+++ b/board/wandboard/spl.c\n@@ -266,17 +266,6 @@ static void ccgr_init(void)\n \twritel(0x000003FF, &ccm->CCGR6);\n }\n \n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\twritel(0x007F007F, &iomux->gpr[6]);\n-\twritel(0x007F007F, &iomux->gpr[7]);\n-}\n-\n static void spl_dram_init(void)\n {\n \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\n", "prefixes": [ "U-Boot" ] }