[{"id":1756339,"web_url":"http://patchwork.ozlabs.org/comment/1756339/","msgid":"<d26b6e49-066d-0043-cc43-3dc2b3aa7301@denx.de>","list_archive_url":null,"date":"2017-08-24T13:02:21","subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","submitter":{"id":5771,"url":"http://patchwork.ozlabs.org/api/people/5771/","name":"Stefano Babic","email":"sbabic@denx.de"},"content":"Hi Breno,\n\nOn 24/08/2017 15:00, Breno Lima wrote:\n> Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,\n> MX6Q and MX6QP processors move it to the soc.c file.\n> \n\nFully agree !\n\nI took a loog a couple of days ago and I saw how much cut&paste code is\nin board/. Thanks, that you did it !\n\n> Signed-off-by: Breno Lima <breno.lima@nxp.com>\n> ---\n>  arch/arm/include/asm/mach-imx/sys_proto.h   |  2 ++\n>  arch/arm/mach-imx/mx6/soc.c                 | 17 +++++++++++++++++\n>  board/bachmann/ot1200/ot1200.c              | 11 -----------\n>  board/barco/platinum/platinum.h             | 11 -----------\n>  board/congatec/cgtqmx6eval/cgtqmx6eval.c    | 11 -----------\n>  board/el/el6x/el6x.c                        | 11 -----------\n>  board/engicam/common/spl.c                  | 11 -----------\n>  board/freescale/mx6sabreauto/mx6sabreauto.c | 17 -----------------\n>  board/freescale/mx6sabresd/mx6sabresd.c     | 17 -----------------\n>  board/gateworks/gw_ventana/gw_ventana_spl.c | 11 -----------\n>  board/kosagi/novena/novena_spl.c            | 11 -----------\n>  board/liebherr/mccmon6/spl.c                | 11 -----------\n>  board/phytec/pcm058/pcm058.c                | 12 ------------\n>  board/phytec/pfla02/pfla02.c                | 11 -----------\n>  board/solidrun/mx6cuboxi/mx6cuboxi.c        | 11 -----------\n>  board/toradex/apalis_imx6/apalis_imx6.c     | 11 -----------\n>  board/toradex/colibri_imx6/colibri_imx6.c   | 11 -----------\n>  board/udoo/udoo_spl.c                       | 11 -----------\n>  board/wandboard/spl.c                       | 11 -----------\n>  19 files changed, 19 insertions(+), 200 deletions(-)\n> \n> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h\n> index 046df62..436ba9a 100644\n> --- a/arch/arm/include/asm/mach-imx/sys_proto.h\n> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h\n> @@ -85,6 +85,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)\n>  }\n>  \n>  u32 imx6_src_get_boot_mode(void);\n> +void gpr_init(void);\n> +\n>  #endif /* CONFIG_MX6 */\n>  \n>  u32 get_nr_cpus(void);\n> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c\n> index 9ede1f5..f8bc05e 100644\n> --- a/arch/arm/mach-imx/mx6/soc.c\n> +++ b/arch/arm/mach-imx/mx6/soc.c\n> @@ -681,6 +681,23 @@ void imx_setup_hdmi(void)\n>  }\n>  #endif\n>  \n> +void gpr_init(void)\n> +{\n> +\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> +\n> +\t/* enable AXI cache for VDOA/VPU/IPU */\n> +\twritel(0xF00000CF, &iomux->gpr[4]);\n> +\tif (is_mx6dqp()) {\n> +\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n> +\t\twritel(0x77177717, &iomux->gpr[6]);\n> +\t\twritel(0x77177717, &iomux->gpr[7]);\n> +\t} else {\n> +\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> +\t\twritel(0x007F007F, &iomux->gpr[6]);\n> +\t\twritel(0x007F007F, &iomux->gpr[7]);\n> +\t}\n> +}\n> +\n>  #ifdef CONFIG_IMX_BOOTAUX\n>  int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)\n>  {\n> diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c\n> index df10d6a..9465cea 100644\n> --- a/board/bachmann/ot1200/ot1200.c\n> +++ b/board/bachmann/ot1200/ot1200.c\n> @@ -169,17 +169,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  int board_early_init_f(void)\n>  {\n>  \tccgr_init();\n> diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h\n> index d3ea8bd..3013ed9 100644\n> --- a/board/barco/platinum/platinum.h\n> +++ b/board/barco/platinum/platinum.h\n> @@ -75,15 +75,4 @@ static inline void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static inline void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  #endif /* _PLATINUM_H_ */\n> diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n> index 8cd0090..2ed66d3 100644\n> --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n> +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n> @@ -955,17 +955,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  /* Define a minimal structure so that the part number can be read via SPL */\n>  struct mfgdata {\n>  \tunsigned char tsize;\n> diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c\n> index 6b98b5c..fb128f5 100644\n> --- a/board/el/el6x/el6x.c\n> +++ b/board/el/el6x/el6x.c\n> @@ -570,17 +570,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  /*\n>   * This section requires the differentiation between iMX6 Sabre boards, but\n>   * for now, it will configure only for the mx6q variant.\n> diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c\n> index a8a7cf3..29a27ce 100644\n> --- a/board/engicam/common/spl.c\n> +++ b/board/engicam/common/spl.c\n> @@ -332,17 +332,6 @@ static void ccgr_init(void)\n>  #endif\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(void)\n>  {\n>  #ifdef CONFIG_MX6QDL\n> diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c\n> index f8f77f6..15ca029 100644\n> --- a/board/freescale/mx6sabreauto/mx6sabreauto.c\n> +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c\n> @@ -798,23 +798,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\tif (is_mx6dqp()) {\n> -\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n> -\t\twritel(0x77177717, &iomux->gpr[6]);\n> -\t\twritel(0x77177717, &iomux->gpr[7]);\n> -\t} else {\n> -\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\t\twritel(0x007F007F, &iomux->gpr[6]);\n> -\t\twritel(0x007F007F, &iomux->gpr[7]);\n> -\t}\n> -}\n> -\n>  static int mx6q_dcd_table[] = {\n>  \t0x020e0798, 0x000C0000,\n>  \t0x020e0758, 0x00000000,\n> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\n> index 9a562b3..5b50bc8 100644\n> --- a/board/freescale/mx6sabresd/mx6sabresd.c\n> +++ b/board/freescale/mx6sabresd/mx6sabresd.c\n> @@ -747,23 +747,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\tif (is_mx6dqp()) {\n> -\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n> -\t\twritel(0x77177717, &iomux->gpr[6]);\n> -\t\twritel(0x77177717, &iomux->gpr[7]);\n> -\t} else {\n> -\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\t\twritel(0x007F007F, &iomux->gpr[6]);\n> -\t\twritel(0x007F007F, &iomux->gpr[7]);\n> -\t}\n> -}\n> -\n>  static int mx6q_dcd_table[] = {\n>  \t0x020e0798, 0x000C0000,\n>  \t0x020e0758, 0x00000000,\n> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c\n> index 9524da7..c2e370b 100644\n> --- a/board/gateworks/gw_ventana/gw_ventana_spl.c\n> +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c\n> @@ -583,17 +583,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  /*\n>   * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n>   * - we have a stack and a place to store GD, both in SRAM\n> diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c\n> index 3645b75..512f06d 100644\n> --- a/board/kosagi/novena/novena_spl.c\n> +++ b/board/kosagi/novena/novena_spl.c\n> @@ -550,17 +550,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  /*\n>   * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n>   * - we have a stack and a place to store GD, both in SRAM\n> diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c\n> index 15844ef..a2f804d 100644\n> --- a/board/liebherr/mccmon6/spl.c\n> +++ b/board/liebherr/mccmon6/spl.c\n> @@ -260,17 +260,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(void)\n>  {\n>  \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\n> diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c\n> index 4257fbc..1538158 100644\n> --- a/board/phytec/pcm058/pcm058.c\n> +++ b/board/phytec/pcm058/pcm058.c\n> @@ -487,18 +487,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n> -\n>  static void spl_dram_init(void)\n>  {\n>  \tstruct mx6_ddr_sysinfo sysinfo = {\n> diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c\n> index 8d2ce63..ec9264d 100644\n> --- a/board/phytec/pfla02/pfla02.c\n> +++ b/board/phytec/pfla02/pfla02.c\n> @@ -550,17 +550,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)\n>  {\n>  \tstruct mx6_ddr_sysinfo sysinfo = {\n> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c\n> index 7e59fb2..986abc5 100644\n> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c\n> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c\n> @@ -581,17 +581,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(int width)\n>  {\n>  \tstruct mx6_ddr_sysinfo sysinfo = {\n> diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c\n> index 2fd9623..ebc6c12 100644\n> --- a/board/toradex/apalis_imx6/apalis_imx6.c\n> +++ b/board/toradex/apalis_imx6/apalis_imx6.c\n> @@ -1160,17 +1160,6 @@ static void ccgr_init(void)\n>  \twritel(0x000000FB, &ccm->ccosr);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void ddr_init(int *table, int size)\n>  {\n>  \tint i;\n> diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c\n> index d30391f..669d912 100644\n> --- a/board/toradex/colibri_imx6/colibri_imx6.c\n> +++ b/board/toradex/colibri_imx6/colibri_imx6.c\n> @@ -1037,17 +1037,6 @@ static void ccgr_init(void)\n>  \twritel(0x000000FB, &ccm->ccosr);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void ddr_init(int *table, int size)\n>  {\n>  \tint i;\n> diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c\n> index e83e7c3..3645969 100644\n> --- a/board/udoo/udoo_spl.c\n> +++ b/board/udoo/udoo_spl.c\n> @@ -211,17 +211,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000FF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(void)\n>  {\n>  \tif (is_cpu_type(MXC_CPU_MX6DL)) {\n> diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c\n> index 47082a8..99a0286 100644\n> --- a/board/wandboard/spl.c\n> +++ b/board/wandboard/spl.c\n> @@ -266,17 +266,6 @@ static void ccgr_init(void)\n>  \twritel(0x000003FF, &ccm->CCGR6);\n>  }\n>  \n> -static void gpr_init(void)\n> -{\n> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n> -\n> -\t/* enable AXI cache for VDOA/VPU/IPU */\n> -\twritel(0xF00000CF, &iomux->gpr[4]);\n> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n> -\twritel(0x007F007F, &iomux->gpr[6]);\n> -\twritel(0x007F007F, &iomux->gpr[7]);\n> -}\n> -\n>  static void spl_dram_init(void)\n>  {\n>  \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\n> \n\nAcked-by: Stefano Babic <sbabic@denx.de>\n\nBest regards,\nStefano Babic","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdPbQ53Wkz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 24 Aug 2017 23:02:42 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 79C44C21E30; Thu, 24 Aug 2017 13:02:41 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 55EA5C21DA9;\n\tThu, 24 Aug 2017 13:02:33 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D37BEC21DA9; Thu, 24 Aug 2017 13:02:31 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby 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[127.0.0.1])\n\tby babic.homelinux.org (Postfix) with ESMTP id 16CCC4540535;\n\tThu, 24 Aug 2017 15:02:25 +0200 (CEST)","from babic.homelinux.org ([127.0.0.1])\n\tby localhost (mail.babic.homelinux.org [127.0.0.1]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id 8qWF5td2EmXc; Thu, 24 Aug 2017 15:02:22 +0200 (CEST)","from [192.168.178.132] (papero.fritz.box [192.168.178.132])\n\tby babic.homelinux.org (Postfix) with ESMTP id 8E0E24540447;\n\tThu, 24 Aug 2017 15:02:21 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=KHOP_BIG_TO_CC,\n\tRCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable\n\tautolearn_force=no version=3.4.0","X-Virus-Scanned":["amavisd-new at mnet-online.de","Debian amavisd-new at babic.homelinux.org"],"To":"Breno Lima <breno.lima@nxp.com>, sbabic@denx.de, fabio.estevam@nxp.com","References":"<1503579616-32426-1-git-send-email-breno.lima@nxp.com>","From":"Stefano Babic <sbabic@denx.de>","Message-ID":"<d26b6e49-066d-0043-cc43-3dc2b3aa7301@denx.de>","Date":"Thu, 24 Aug 2017 15:02:21 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1503579616-32426-1-git-send-email-breno.lima@nxp.com>","Content-Language":"de-DE","Cc":"marex@denx.de, albert.u.boot@aribaud.net, ping.bai@nxp.com,\n\totavio@ossystems.com.br, stefan.agner@toradex.com, u-boot@lists.denx.de, \n\tmax.krummenacher@toradex.com, sr@denx.de","Subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion <u-boot.lists.denx.de>","List-Unsubscribe":"<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>","List-Archive":"<http://lists.denx.de/pipermail/u-boot/>","List-Post":"<mailto:u-boot@lists.denx.de>","List-Help":"<mailto:u-boot-request@lists.denx.de?subject=help>","List-Subscribe":"<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" <u-boot-bounces@lists.denx.de>"}},{"id":1756340,"web_url":"http://patchwork.ozlabs.org/comment/1756340/","msgid":"<9cb736da-2bee-c168-7b53-435d97cf9782@denx.de>","list_archive_url":null,"date":"2017-08-24T13:04:31","subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","submitter":{"id":70701,"url":"http://patchwork.ozlabs.org/api/people/70701/","name":"Lukasz Majewski","email":"lukma@denx.de"},"content":"On 08/24/2017 03:02 PM, Stefano Babic wrote:\n> Hi Breno,\n>\n> On 24/08/2017 15:00, Breno Lima wrote:\n>> Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,\n>> MX6Q and MX6QP processors move it to the soc.c file.\n>>\n>\n> Fully agree !\n>\n> I took a loog a couple of days ago and I saw how much cut&paste code is\n> in board/. Thanks, that you did it !\n>\n>> Signed-off-by: Breno Lima <breno.lima@nxp.com>\n>> ---\n>>  arch/arm/include/asm/mach-imx/sys_proto.h   |  2 ++\n>>  arch/arm/mach-imx/mx6/soc.c                 | 17 +++++++++++++++++\n>>  board/bachmann/ot1200/ot1200.c              | 11 -----------\n>>  board/barco/platinum/platinum.h             | 11 -----------\n>>  board/congatec/cgtqmx6eval/cgtqmx6eval.c    | 11 -----------\n>>  board/el/el6x/el6x.c                        | 11 -----------\n>>  board/engicam/common/spl.c                  | 11 -----------\n>>  board/freescale/mx6sabreauto/mx6sabreauto.c | 17 -----------------\n>>  board/freescale/mx6sabresd/mx6sabresd.c     | 17 -----------------\n>>  board/gateworks/gw_ventana/gw_ventana_spl.c | 11 -----------\n>>  board/kosagi/novena/novena_spl.c            | 11 -----------\n>>  board/liebherr/mccmon6/spl.c                | 11 -----------\n>>  board/phytec/pcm058/pcm058.c                | 12 ------------\n>>  board/phytec/pfla02/pfla02.c                | 11 -----------\n>>  board/solidrun/mx6cuboxi/mx6cuboxi.c        | 11 -----------\n>>  board/toradex/apalis_imx6/apalis_imx6.c     | 11 -----------\n>>  board/toradex/colibri_imx6/colibri_imx6.c   | 11 -----------\n>>  board/udoo/udoo_spl.c                       | 11 -----------\n>>  board/wandboard/spl.c                       | 11 -----------\n>>  19 files changed, 19 insertions(+), 200 deletions(-)\n>>\n>> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h\n>> index 046df62..436ba9a 100644\n>> --- a/arch/arm/include/asm/mach-imx/sys_proto.h\n>> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h\n>> @@ -85,6 +85,8 @@ static inline u8 imx6_is_bmode_from_gpr9(void)\n>>  }\n>>\n>>  u32 imx6_src_get_boot_mode(void);\n>> +void gpr_init(void);\n>> +\n>>  #endif /* CONFIG_MX6 */\n>>\n>>  u32 get_nr_cpus(void);\n>> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c\n>> index 9ede1f5..f8bc05e 100644\n>> --- a/arch/arm/mach-imx/mx6/soc.c\n>> +++ b/arch/arm/mach-imx/mx6/soc.c\n>> @@ -681,6 +681,23 @@ void imx_setup_hdmi(void)\n>>  }\n>>  #endif\n>>\n>> +void gpr_init(void)\n>> +{\n>> +\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> +\n>> +\t/* enable AXI cache for VDOA/VPU/IPU */\n>> +\twritel(0xF00000CF, &iomux->gpr[4]);\n>> +\tif (is_mx6dqp()) {\n>> +\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n>> +\t\twritel(0x77177717, &iomux->gpr[6]);\n>> +\t\twritel(0x77177717, &iomux->gpr[7]);\n>> +\t} else {\n>> +\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> +\t\twritel(0x007F007F, &iomux->gpr[6]);\n>> +\t\twritel(0x007F007F, &iomux->gpr[7]);\n>> +\t}\n>> +}\n>> +\n>>  #ifdef CONFIG_IMX_BOOTAUX\n>>  int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)\n>>  {\n>> diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c\n>> index df10d6a..9465cea 100644\n>> --- a/board/bachmann/ot1200/ot1200.c\n>> +++ b/board/bachmann/ot1200/ot1200.c\n>> @@ -169,17 +169,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  int board_early_init_f(void)\n>>  {\n>>  \tccgr_init();\n>> diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h\n>> index d3ea8bd..3013ed9 100644\n>> --- a/board/barco/platinum/platinum.h\n>> +++ b/board/barco/platinum/platinum.h\n>> @@ -75,15 +75,4 @@ static inline void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static inline void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  #endif /* _PLATINUM_H_ */\n>> diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n>> index 8cd0090..2ed66d3 100644\n>> --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n>> +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c\n>> @@ -955,17 +955,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  /* Define a minimal structure so that the part number can be read via SPL */\n>>  struct mfgdata {\n>>  \tunsigned char tsize;\n>> diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c\n>> index 6b98b5c..fb128f5 100644\n>> --- a/board/el/el6x/el6x.c\n>> +++ b/board/el/el6x/el6x.c\n>> @@ -570,17 +570,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  /*\n>>   * This section requires the differentiation between iMX6 Sabre boards, but\n>>   * for now, it will configure only for the mx6q variant.\n>> diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c\n>> index a8a7cf3..29a27ce 100644\n>> --- a/board/engicam/common/spl.c\n>> +++ b/board/engicam/common/spl.c\n>> @@ -332,17 +332,6 @@ static void ccgr_init(void)\n>>  #endif\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(void)\n>>  {\n>>  #ifdef CONFIG_MX6QDL\n>> diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c\n>> index f8f77f6..15ca029 100644\n>> --- a/board/freescale/mx6sabreauto/mx6sabreauto.c\n>> +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c\n>> @@ -798,23 +798,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\tif (is_mx6dqp()) {\n>> -\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n>> -\t\twritel(0x77177717, &iomux->gpr[6]);\n>> -\t\twritel(0x77177717, &iomux->gpr[7]);\n>> -\t} else {\n>> -\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\t\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\t\twritel(0x007F007F, &iomux->gpr[7]);\n>> -\t}\n>> -}\n>> -\n>>  static int mx6q_dcd_table[] = {\n>>  \t0x020e0798, 0x000C0000,\n>>  \t0x020e0758, 0x00000000,\n>> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\n>> index 9a562b3..5b50bc8 100644\n>> --- a/board/freescale/mx6sabresd/mx6sabresd.c\n>> +++ b/board/freescale/mx6sabresd/mx6sabresd.c\n>> @@ -747,23 +747,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\tif (is_mx6dqp()) {\n>> -\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n>> -\t\twritel(0x77177717, &iomux->gpr[6]);\n>> -\t\twritel(0x77177717, &iomux->gpr[7]);\n>> -\t} else {\n>> -\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\t\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\t\twritel(0x007F007F, &iomux->gpr[7]);\n>> -\t}\n>> -}\n>> -\n>>  static int mx6q_dcd_table[] = {\n>>  \t0x020e0798, 0x000C0000,\n>>  \t0x020e0758, 0x00000000,\n>> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c\n>> index 9524da7..c2e370b 100644\n>> --- a/board/gateworks/gw_ventana/gw_ventana_spl.c\n>> +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c\n>> @@ -583,17 +583,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  /*\n>>   * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n>>   * - we have a stack and a place to store GD, both in SRAM\n>> diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c\n>> index 3645b75..512f06d 100644\n>> --- a/board/kosagi/novena/novena_spl.c\n>> +++ b/board/kosagi/novena/novena_spl.c\n>> @@ -550,17 +550,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  /*\n>>   * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n>>   * - we have a stack and a place to store GD, both in SRAM\n>> diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c\n>> index 15844ef..a2f804d 100644\n>> --- a/board/liebherr/mccmon6/spl.c\n>> +++ b/board/liebherr/mccmon6/spl.c\n>> @@ -260,17 +260,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(void)\n>>  {\n>>  \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\n>> diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c\n>> index 4257fbc..1538158 100644\n>> --- a/board/phytec/pcm058/pcm058.c\n>> +++ b/board/phytec/pcm058/pcm058.c\n>> @@ -487,18 +487,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>> -\n>>  static void spl_dram_init(void)\n>>  {\n>>  \tstruct mx6_ddr_sysinfo sysinfo = {\n>> diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c\n>> index 8d2ce63..ec9264d 100644\n>> --- a/board/phytec/pfla02/pfla02.c\n>> +++ b/board/phytec/pfla02/pfla02.c\n>> @@ -550,17 +550,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr)\n>>  {\n>>  \tstruct mx6_ddr_sysinfo sysinfo = {\n>> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c\n>> index 7e59fb2..986abc5 100644\n>> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c\n>> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c\n>> @@ -581,17 +581,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(int width)\n>>  {\n>>  \tstruct mx6_ddr_sysinfo sysinfo = {\n>> diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c\n>> index 2fd9623..ebc6c12 100644\n>> --- a/board/toradex/apalis_imx6/apalis_imx6.c\n>> +++ b/board/toradex/apalis_imx6/apalis_imx6.c\n>> @@ -1160,17 +1160,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000000FB, &ccm->ccosr);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void ddr_init(int *table, int size)\n>>  {\n>>  \tint i;\n>> diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c\n>> index d30391f..669d912 100644\n>> --- a/board/toradex/colibri_imx6/colibri_imx6.c\n>> +++ b/board/toradex/colibri_imx6/colibri_imx6.c\n>> @@ -1037,17 +1037,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000000FB, &ccm->ccosr);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void ddr_init(int *table, int size)\n>>  {\n>>  \tint i;\n>> diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c\n>> index e83e7c3..3645969 100644\n>> --- a/board/udoo/udoo_spl.c\n>> +++ b/board/udoo/udoo_spl.c\n>> @@ -211,17 +211,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000FF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(void)\n>>  {\n>>  \tif (is_cpu_type(MXC_CPU_MX6DL)) {\n>> diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c\n>> index 47082a8..99a0286 100644\n>> --- a/board/wandboard/spl.c\n>> +++ b/board/wandboard/spl.c\n>> @@ -266,17 +266,6 @@ static void ccgr_init(void)\n>>  \twritel(0x000003FF, &ccm->CCGR6);\n>>  }\n>>\n>> -static void gpr_init(void)\n>> -{\n>> -\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n>> -\n>> -\t/* enable AXI cache for VDOA/VPU/IPU */\n>> -\twritel(0xF00000CF, &iomux->gpr[4]);\n>> -\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n>> -\twritel(0x007F007F, &iomux->gpr[6]);\n>> -\twritel(0x007F007F, &iomux->gpr[7]);\n>> -}\n>> -\n>>  static void spl_dram_init(void)\n>>  {\n>>  \tif (is_cpu_type(MXC_CPU_MX6SOLO)) {\n>>\n>\n> Acked-by: Stefano Babic <sbabic@denx.de>\n>\n> Best regards,\n> Stefano Babic\n>\n\nReviewed-by: Lukasz Majewski <lukma@denx.de>","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdPdn38zYz9sR9\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 24 Aug 2017 23:04:45 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 0C458C21E61; Thu, 24 Aug 2017 13:04:43 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id AF167C21DA9;\n\tThu, 24 Aug 2017 13:04:38 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 134EBC21DA9; Thu, 24 Aug 2017 13:04:37 +0000 (UTC)","from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id 80DE9C21D79\n\tfor <u-boot@lists.denx.de>; Thu, 24 Aug 2017 13:04:36 +0000 (UTC)","from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3xdPdc0hNCz1qqkr;\n\tThu, 24 Aug 2017 15:04:36 +0200 (CEST)","from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3xdPdb4Wy0z3jgYm;\n\tThu, 24 Aug 2017 15:04:35 +0200 (CEST)","from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id ObbGBgJG_4ck; Thu, 24 Aug 2017 15:04:32 +0200 (CEST)","from [192.168.2.222] (89-77-92-62.dynamic.chello.pl [89.77.92.62])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tThu, 24 Aug 2017 15:04:31 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=KHOP_BIG_TO_CC,\n\tRCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable\n\tautolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"rTF3jZfamzklLmxKkd1HafUfsnjCRzYKfXtoMMoX6XE=","To":"Stefano Babic <sbabic@denx.de>, Breno Lima <breno.lima@nxp.com>,\n\tfabio.estevam@nxp.com","References":"<1503579616-32426-1-git-send-email-breno.lima@nxp.com>\n\t<d26b6e49-066d-0043-cc43-3dc2b3aa7301@denx.de>","From":"=?UTF-8?Q?=c5=81ukasz_Majewski?= <lukma@denx.de>","Organization":"DENX","Message-ID":"<9cb736da-2bee-c168-7b53-435d97cf9782@denx.de>","Date":"Thu, 24 Aug 2017 15:04:31 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<d26b6e49-066d-0043-cc43-3dc2b3aa7301@denx.de>","Cc":"marex@denx.de, albert.u.boot@aribaud.net, ping.bai@nxp.com,\n\totavio@ossystems.com.br, stefan.agner@toradex.com, u-boot@lists.denx.de, \n\tmax.krummenacher@toradex.com, sr@denx.de","Subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion <u-boot.lists.denx.de>","List-Unsubscribe":"<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>","List-Archive":"<http://lists.denx.de/pipermail/u-boot/>","List-Post":"<mailto:u-boot@lists.denx.de>","List-Help":"<mailto:u-boot-request@lists.denx.de?subject=help>","List-Subscribe":"<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" <u-boot-bounces@lists.denx.de>"}},{"id":1756341,"web_url":"http://patchwork.ozlabs.org/comment/1756341/","msgid":"<CAOMZO5CLN1PQC7=iOzxGuHAwLOZ6uBsG_cjTWJcaGFe8SWOCPA@mail.gmail.com>","list_archive_url":null,"date":"2017-08-24T13:06:09","subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","submitter":{"id":6978,"url":"http://patchwork.ozlabs.org/api/people/6978/","name":"Fabio Estevam","email":"festevam@gmail.com"},"content":"Hi Breno,\n\nOn Thu, Aug 24, 2017 at 10:00 AM, Breno Lima <breno.lima@nxp.com> wrote:\n> Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D,\n> MX6Q and MX6QP processors move it to the soc.c file.\n>\n> Signed-off-by: Breno Lima <breno.lima@nxp.com>\n> ---\n>  arch/arm/include/asm/mach-imx/sys_proto.h   |  2 ++\n>  arch/arm/mach-imx/mx6/soc.c                 | 17 +++++++++++++++++\n>  board/bachmann/ot1200/ot1200.c              | 11 -----------\n>  board/barco/platinum/platinum.h             | 11 -----------\n>  board/congatec/cgtqmx6eval/cgtqmx6eval.c    | 11 -----------\n>  board/el/el6x/el6x.c                        | 11 -----------\n>  board/engicam/common/spl.c                  | 11 -----------\n>  board/freescale/mx6sabreauto/mx6sabreauto.c | 17 -----------------\n>  board/freescale/mx6sabresd/mx6sabresd.c     | 17 -----------------\n>  board/gateworks/gw_ventana/gw_ventana_spl.c | 11 -----------\n>  board/kosagi/novena/novena_spl.c            | 11 -----------\n>  board/liebherr/mccmon6/spl.c                | 11 -----------\n>  board/phytec/pcm058/pcm058.c                | 12 ------------\n>  board/phytec/pfla02/pfla02.c                | 11 -----------\n>  board/solidrun/mx6cuboxi/mx6cuboxi.c        | 11 -----------\n>  board/toradex/apalis_imx6/apalis_imx6.c     | 11 -----------\n>  board/toradex/colibri_imx6/colibri_imx6.c   | 11 -----------\n>  board/udoo/udoo_spl.c                       | 11 -----------\n>  board/wandboard/spl.c                       | 11 -----------\n>  19 files changed, 19 insertions(+), 200 deletions(-)\n\nNice statistics :-) Thanks for the cleanup:\n\nReviewed-by: Fabio Estevam <fabio.estevam@nxp.com>","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"OSBesYBE\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xdPgh1Hhwz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 24 Aug 2017 23:06:24 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E02B6C21E27; Thu, 24 Aug 2017 13:06:17 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id F312CC21DA9;\n\tThu, 24 Aug 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2017 10:06:09 -0300","Message-ID":"<CAOMZO5CLN1PQC7=iOzxGuHAwLOZ6uBsG_cjTWJcaGFe8SWOCPA@mail.gmail.com>","To":"Breno Lima <breno.lima@nxp.com>","Cc":"Marek Vasut <marex@denx.de>, Albert ARIBAUD <albert.u.boot@aribaud.net>, \n\tPing Bai <ping.bai@nxp.com>, Otavio Salvador <otavio@ossystems.com.br>, \n\tStefan Agner <stefan.agner@toradex.com>,\n\tU-Boot-Denx <u-boot@lists.denx.de>, \n\tMax Krummenacher <max.krummenacher@toradex.com>,\n\tFabio Estevam <fabio.estevam@nxp.com>, Stefan Roese <sr@denx.de>","Subject":"Re: [U-Boot] [PATCH] imx: imx6: Move gpr_init() function to soc.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion 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