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GET /api/patches/804859/?format=api
{ "id": 804859, "url": "http://patchwork.ozlabs.org/api/patches/804859/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503473218-16773-1-git-send-email-andy.yan@rock-chips.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503473218-16773-1-git-send-email-andy.yan@rock-chips.com>", "list_archive_url": null, "date": "2017-08-23T07:26:58", "name": "[U-Boot] rockchip: clk: rk3368: always run rkclk_init when driver probe", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d9aeb70abfa56d3672d64d1295b54af1c18aa915", "submitter": { "id": 65124, "url": "http://patchwork.ozlabs.org/api/people/65124/?format=api", "name": "Andy Yan", "email": "andy.yan@rock-chips.com" }, "delegate": { "id": 69486, "url": "http://patchwork.ozlabs.org/api/users/69486/?format=api", "username": "ptomsich", "first_name": "Philipp", "last_name": "Tomsich", "email": "philipp.tomsich@theobroma-systems.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503473218-16773-1-git-send-email-andy.yan@rock-chips.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804859/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804859/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcfC75YkPz9s9Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 17:27:30 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 45944C21E56; Wed, 23 Aug 2017 07:27:23 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 916CEC21DCE;\n\tWed, 23 Aug 2017 07:27:19 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 12909C21DCE; Wed, 23 Aug 2017 07:27:18 +0000 (UTC)", "from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138])\n\tby lists.denx.de (Postfix) with ESMTPS id ABB68C21DA5\n\tfor <u-boot@lists.denx.de>; Wed, 23 Aug 2017 07:27:16 +0000 (UTC)", "from andy.yan?rock-chips.com (unknown [192.168.167.156])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 04C8179CE\n\tfor <u-boot@lists.denx.de>; Wed, 23 Aug 2017 15:27:05 +0800 (CST)", "from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 53A2D308;\n\tWed, 23 Aug 2017 15:27:05 +0800 (CST)", "from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 260268VX7Z6;\n\tWed, 23 Aug 2017 15:27:06 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "*", "X-Spam-Status": "No, score=1.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET,\n\tRCVD_IN_DNSWL_NONE autolearn=no autolearn_force=no version=3.4.0", "X-263anti-spam": "KSV:0;", "X-MAIL-GRAY": "0", "X-MAIL-DELIVERY": "1", "X-KSVirus-check": "0", "X-ABS-CHECKED": "4", "X-RL-SENDER": "andy.yan@rock-chips.com", "X-FST-TO": "philipp.tomsich@theobroma-systems.com", "X-SENDER-IP": "58.22.7.114", "X-LOGIN-NAME": "andy.yan@rock-chips.com", "X-UNIQUE-TAG": "<ff09e4aed879a1a2fb5ce379017541bd>", "X-ATTACHMENT-NUM": "0", "X-SENDER": "yxj@rock-chips.com", "X-DNS-TYPE": "0", "From": "Andy Yan <andy.yan@rock-chips.com>", "To": "philipp.tomsich@theobroma-systems.com", "Date": "Wed, 23 Aug 2017 15:26:58 +0800", "Message-Id": "<1503473218-16773-1-git-send-email-andy.yan@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "Cc": "u-boot@lists.denx.de, Andy Yan <andy.yan@rock-chips.com>", "Subject": "[U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init when\n\tdriver probe", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "commit 4bebf94e8544(\"rockchip: clk: rk3368: do not change\nCPLL/GPLL before returning to BROM\") limits the pll can only\nbe setup in SPL stage, but there are still some rk3368 based\nboards have not use SPL yet, so they need run rkclk_init to\nsetup the pll in full u-boot stage, otherwise the clk_set_rate\nfunction will run into wrong logic, because it assume that all\nthe pll have been set to the desired frequency.\n\nSigned-off-by: Andy Yan <andy.yan@rock-chips.com>\n---\n\n drivers/clk/rockchip/clk_rk3368.c | 10 ++--------\n 1 file changed, 2 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\nindex 2be1f57..ee754f0 100644\n--- a/drivers/clk/rockchip/clk_rk3368.c\n+++ b/drivers/clk/rockchip/clk_rk3368.c\n@@ -47,14 +47,12 @@ struct pll_div {\n \t\t (_nr * _no) == hz, #hz \"Hz cannot be hit with PLL \" \\\n \t\t \"divisors on line \" __stringify(__LINE__));\n \n-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);\n static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);\n #if !defined(CONFIG_TPL_BUILD)\n static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);\n static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);\n #endif\n-#endif\n \n static ulong rk3368_clk_get_rate(struct clk *clk);\n \n@@ -85,7 +83,6 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,\n \t}\n }\n \n-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n \t\t\t const struct pll_div *div)\n {\n@@ -125,9 +122,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n \n \treturn 0;\n }\n-#endif\n \n-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n static void rkclk_init(struct rk3368_cru *cru)\n {\n \tu32 apllb, aplll, dpll, cpll, gpll;\n@@ -152,7 +147,7 @@ static void rkclk_init(struct rk3368_cru *cru)\n \tdebug(\"%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\\n\",\n \t __func__, apllb, aplll, dpll, cpll, gpll);\n }\n-#endif\n+\n \n #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)\n static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)\n@@ -473,9 +468,8 @@ static int rk3368_clk_probe(struct udevice *dev)\n \n \tpriv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);\n #endif\n-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n+\n \trkclk_init(priv->cru);\n-#endif\n \n \treturn 0;\n }\n", "prefixes": [ "U-Boot" ] }