[{"id":1758307,"web_url":"http://patchwork.ozlabs.org/comment/1758307/","msgid":"","list_archive_url":null,"date":"2017-08-27T20:10:01","subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi Andy\n\nOn 23 August 2017 at 01:26, Andy Yan wrote:\n> commit 4bebf94e8544(\"rockchip: clk: rk3368: do not change\n> CPLL/GPLL before returning to BROM\") limits the pll can only\n> be setup in SPL stage, but there are still some rk3368 based\n> boards have not use SPL yet, so they need run rkclk_init to\n> setup the pll in full u-boot stage, otherwise the clk_set_rate\n> function will run into wrong logic, because it assume that all\n> the pll have been set to the desired frequency.\n>\n> Signed-off-by: Andy Yan \n> ---\n>\n> drivers/clk/rockchip/clk_rk3368.c | 10 ++--------\n> 1 file changed, 2 insertions(+), 8 deletions(-)\n>\n> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\n> index 2be1f57..ee754f0 100644\n> --- a/drivers/clk/rockchip/clk_rk3368.c\n> +++ b/drivers/clk/rockchip/clk_rk3368.c\n> @@ -47,14 +47,12 @@ struct pll_div {\n> (_nr * _no) == hz, #hz \"Hz cannot be hit with PLL \" \\\n> \"divisors on line \" __stringify(__LINE__));\n>\n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);\n> static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);\n> #if !defined(CONFIG_TPL_BUILD)\n> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);\n> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);\n> #endif\n> -#endif\n>\n> static ulong rk3368_clk_get_rate(struct clk *clk);\n>\n> @@ -85,7 +83,6 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,\n> }\n> }\n>\n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n> const struct pll_div *div)\n> {\n> @@ -125,9 +122,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n>\n> return 0;\n> }\n> -#endif\n>\n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static void rkclk_init(struct rk3368_cru *cru)\n> {\n> u32 apllb, aplll, dpll, cpll, gpll;\n> @@ -152,7 +147,7 @@ static void rkclk_init(struct rk3368_cru *cru)\n> debug(\"%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\\n\",\n> __func__, apllb, aplll, dpll, cpll, gpll);\n> }\n> -#endif\n> +\n>\n> #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)\n> static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)\n> @@ -473,9 +468,8 @@ static int rk3368_clk_probe(struct udevice *dev)\n>\n> priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);\n> #endif\n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n\nCan you please use if() instead of #if? Then you can drop the #if above.\n\n> +\n> rkclk_init(priv->cru);\n> -#endif\n>\n> return 0;\n> }\n> --\n> 2.7.4\n>\n>\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"hi7NWF6J\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=chromium.org header.i=@chromium.org\n\theader.b=\"CI1ftm8j\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgR4313dQz9s8V\n\tfor ;\n\tMon, 28 Aug 2017 06:16:03 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid CA735C2232C; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1758313,"web_url":"http://patchwork.ozlabs.org/comment/1758313/","msgid":"<70B4A699-CEE9-4403-8D30-2FD5CD512190@theobroma-systems.com>","list_archive_url":null,"date":"2017-08-27T20:21:06","subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 23 Aug 2017, at 09:26, Andy Yan wrote:\n> \n> commit 4bebf94e8544(\"rockchip: clk: rk3368: do not change\n> CPLL/GPLL before returning to BROM\") limits the pll can only\n> be setup in SPL stage, but there are still some rk3368 based\n> boards have not use SPL yet, so they need run rkclk_init to\n> setup the pll in full u-boot stage, otherwise the clk_set_rate\n> function will run into wrong logic, because it assume that all\n> the pll have been set to the desired frequency.\n\nIf SPL is enabled, rkclk_init should not be called from the full\nU-Boot, though. I.e. we’ll need an appropriate conditional\ntest to check whether SPL is enabled or not...\n\n> Signed-off-by: Andy Yan \n> ---\n> \n> drivers/clk/rockchip/clk_rk3368.c | 10 ++--------\n> 1 file changed, 2 insertions(+), 8 deletions(-)\n> \n> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\n> index 2be1f57..ee754f0 100644\n> --- a/drivers/clk/rockchip/clk_rk3368.c\n> +++ b/drivers/clk/rockchip/clk_rk3368.c\n> @@ -47,14 +47,12 @@ struct pll_div {\n> \t\t (_nr * _no) == hz, #hz \"Hz cannot be hit with PLL \" \\\n> \t\t \"divisors on line \" __stringify(__LINE__));\n> \n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);\n> static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);\n> #if !defined(CONFIG_TPL_BUILD)\n> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);\n> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);\n> #endif\n> -#endif\n> \n> static ulong rk3368_clk_get_rate(struct clk *clk);\n> \n> @@ -85,7 +83,6 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,\n> \t}\n> }\n> \n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n> \t\t\t const struct pll_div *div)\n> {\n> @@ -125,9 +122,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n> \n> \treturn 0;\n> }\n> -#endif\n> \n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> static void rkclk_init(struct rk3368_cru *cru)\n> {\n> \tu32 apllb, aplll, dpll, cpll, gpll;\n> @@ -152,7 +147,7 @@ static void rkclk_init(struct rk3368_cru *cru)\n> \tdebug(\"%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\\n\",\n> \t __func__, apllb, aplll, dpll, cpll, gpll);\n> }\n> -#endif\n> +\n> \n> #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)\n> static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)\n> @@ -473,9 +468,8 @@ static int rk3368_clk_probe(struct udevice *dev)\n> \n> \tpriv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);\n> #endif\n> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n> +\n> \trkclk_init(priv->cru);\n> -#endif\n> \n> \treturn 0;\n> }\n> -- \n> 2.7.4\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgRNt6vyGz9sD5\n\tfor ;\n\tMon, 28 Aug 2017 06:30:38 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C541AC222E3; Sun, 27 Aug 2017 20:27:04 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A5C3BC2231F;\n\tSun, 27 Aug 2017 20:27:01 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 748DAC22316; Sun, 27 Aug 2017 20:21:10 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 62A25C222BB\n\tfor ; Sun, 27 Aug 2017 20:21:10 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:56541\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dm43P-0003ll-0e; Sun, 27 Aug 2017 22:21:07 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 8.2 \\(2104\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<1503473218-16773-1-git-send-email-andy.yan@rock-chips.com>","Date":"Sun, 27 Aug 2017 22:21:06 +0200","Message-Id":"<70B4A699-CEE9-4403-8D30-2FD5CD512190@theobroma-systems.com>","References":"<1503473218-16773-1-git-send-email-andy.yan@rock-chips.com>","To":"Andy Yan ","X-Mailer":"Apple Mail (2.2104)","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1760812,"web_url":"http://patchwork.ozlabs.org/comment/1760812/","msgid":"<301399da-925c-3648-5380-49f9989237be@rock-chips.com>","list_archive_url":null,"date":"2017-08-31T10:25:15","subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","submitter":{"id":65124,"url":"http://patchwork.ozlabs.org/api/people/65124/","name":"Andy Yan","email":"andy.yan@rock-chips.com"},"content":"Hi Philipp:\n\n\nOn 2017年08月28日 04:21, Dr. Philipp Tomsich wrote:\n>> On 23 Aug 2017, at 09:26, Andy Yan wrote:\n>>\n>> commit 4bebf94e8544(\"rockchip: clk: rk3368: do not change\n>> CPLL/GPLL before returning to BROM\") limits the pll can only\n>> be setup in SPL stage, but there are still some rk3368 based\n>> boards have not use SPL yet, so they need run rkclk_init to\n>> setup the pll in full u-boot stage, otherwise the clk_set_rate\n>> function will run into wrong logic, because it assume that all\n>> the pll have been set to the desired frequency.\n> If SPL is enabled, rkclk_init should not be called from the full\n> U-Boot, though. I.e. we’ll need an appropriate conditional\n> test to check whether SPL is enabled or not...\n\n Do you have any ideas here?\n\n\n>\n>> Signed-off-by: Andy Yan \n>> ---\n>>\n>> drivers/clk/rockchip/clk_rk3368.c | 10 ++--------\n>> 1 file changed, 2 insertions(+), 8 deletions(-)\n>>\n>> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\n>> index 2be1f57..ee754f0 100644\n>> --- a/drivers/clk/rockchip/clk_rk3368.c\n>> +++ b/drivers/clk/rockchip/clk_rk3368.c\n>> @@ -47,14 +47,12 @@ struct pll_div {\n>> \t\t (_nr * _no) == hz, #hz \"Hz cannot be hit with PLL \" \\\n>> \t\t \"divisors on line \" __stringify(__LINE__));\n>>\n>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>> static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);\n>> static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);\n>> #if !defined(CONFIG_TPL_BUILD)\n>> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);\n>> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);\n>> #endif\n>> -#endif\n>>\n>> static ulong rk3368_clk_get_rate(struct clk *clk);\n>>\n>> @@ -85,7 +83,6 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,\n>> \t}\n>> }\n>>\n>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>> static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n>> \t\t\t const struct pll_div *div)\n>> {\n>> @@ -125,9 +122,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,\n>> seamless\n>> \treturn 0;\n>> }\n>> -#endif\n>>\n>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>> static void rkclk_init(struct rk3368_cru *cru)\n>> {\n>> \tu32 apllb, aplll, dpll, cpll, gpll;\n>> @@ -152,7 +147,7 @@ static void rkclk_init(struct rk3368_cru *cru)\n>> \tdebug(\"%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\\n\",\n>> \t __func__, apllb, aplll, dpll, cpll, gpll);\n>> }\n>> -#endif\n>> +\n>>\n>> #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)\n>> static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)\n>> @@ -473,9 +468,8 @@ static int rk3368_clk_probe(struct udevice *dev)\n>>\n>> \tpriv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);\n>> #endif\n>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>> +\n>> \trkclk_init(priv->cru);\n>> -#endif\n>>\n>> \treturn 0;\n>> }\n>> -- \n>> 2.7.4\n>>\n>>\n>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjdmr5bXwz9sPt\n\tfor ;\n\tThu, 31 Aug 2017 20:25:31 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 7B8F9C21D7B; Thu, 31 Aug 2017 10:25:25 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9B753C21C59;\n\tThu, 31 Aug 2017 10:25:23 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid AA62DC21C59; Thu, 31 Aug 2017 10:25:21 +0000 (UTC)","from regular1.263xmail.com (regular1.263xmail.com [211.150.99.139])\n\tby lists.denx.de (Postfix) with ESMTPS id 92F40C21C51\n\tfor ; Thu, 31 Aug 2017 10:25:20 +0000 (UTC)","from andy.yan?rock-chips.com (unknown [192.168.167.153])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 89A8254A9\n\tfor ; Thu, 31 Aug 2017 18:25:14 +0800 (CST)","from [172.16.12.215] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id BE7F73BE;\n\tThu, 31 Aug 2017 18:25:15 +0800 (CST)","from [172.16.12.215] (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 3126455C790;\n\tThu, 31 Aug 2017 18:25:16 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"andy.yan@rock-chips.com","X-FST-TO":"u-boot@lists.denx.de","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"andy.yan@rock-chips.com","X-UNIQUE-TAG":"","X-ATTACHMENT-NUM":"0","X-SENDER":"yxj@rock-chips.com","X-DNS-TYPE":"0","To":"\"Dr. Philipp Tomsich\" ","References":"<1503473218-16773-1-git-send-email-andy.yan@rock-chips.com>\n\t<70B4A699-CEE9-4403-8D30-2FD5CD512190@theobroma-systems.com>","From":"Andy Yan ","Message-ID":"<301399da-925c-3648-5380-49f9989237be@rock-chips.com>","Date":"Thu, 31 Aug 2017 18:25:15 +0800","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<70B4A699-CEE9-4403-8D30-2FD5CD512190@theobroma-systems.com>","Content-Language":"en-US","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776103,"web_url":"http://patchwork.ozlabs.org/comment/1776103/","msgid":"<7df2f350-cd2a-71d7-1ff2-451d3060c6e5@rock-chips.com>","list_archive_url":null,"date":"2017-09-27T07:54:51","subject":"Re: [U-Boot] [PATCH] rockchip: clk: rk3368: always run rkclk_init\n\twhen driver probe","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"content":"Hi Philipp,\n\n\nOn 08/31/2017 06:25 PM, Andy Yan wrote:\n> Hi Philipp:\n>\n>\n> On 2017年08月28日 04:21, Dr. Philipp Tomsich wrote:\n>>> On 23 Aug 2017, at 09:26, Andy Yan wrote:\n>>>\n>>> commit 4bebf94e8544(\"rockchip: clk: rk3368: do not change\n>>> CPLL/GPLL before returning to BROM\") limits the pll can only\n>>> be setup in SPL stage, but there are still some rk3368 based\n>>> boards have not use SPL yet, so they need run rkclk_init to\n>>> setup the pll in full u-boot stage, otherwise the clk_set_rate\n>>> function will run into wrong logic, because it assume that all\n>>> the pll have been set to the desired frequency.\n>> If SPL is enabled, rkclk_init should not be called from the full\n>> U-Boot, though. I.e. we’ll need an appropriate conditional\n>> test to check whether SPL is enabled or not...\n>\n> Do you have any ideas here?\n\nThere should have some memory could be pass from SPL (optionally via \nATF/OPTEE)\nto U-Boot, may including information like this,\n- hardware module info/status already known in previous stage, like dram \ncap in sysreg,\n- the boot device, boot rom boot from SD card, then U-Boot prefer to \nboot from SD card,\n- Android O, there is a A/B slot select, if we detect it in SPL, then we \ncan pass it to U-Boot\nand etc.\n\nMaybe we can have a vendor defined structure locate in a reserved memory \nlike boot0hook?\n\nThanks,\n- Kever\n>\n>\n>>\n>>> Signed-off-by: Andy Yan \n>>> ---\n>>>\n>>> drivers/clk/rockchip/clk_rk3368.c | 10 ++--------\n>>> 1 file changed, 2 insertions(+), 8 deletions(-)\n>>>\n>>> diff --git a/drivers/clk/rockchip/clk_rk3368.c \n>>> b/drivers/clk/rockchip/clk_rk3368.c\n>>> index 2be1f57..ee754f0 100644\n>>> --- a/drivers/clk/rockchip/clk_rk3368.c\n>>> +++ b/drivers/clk/rockchip/clk_rk3368.c\n>>> @@ -47,14 +47,12 @@ struct pll_div {\n>>> (_nr * _no) == hz, #hz \"Hz cannot be hit with PLL \" \\\n>>> \"divisors on line \" __stringify(__LINE__));\n>>>\n>>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>>> static const struct pll_div apll_l_init_cfg = \n>>> PLL_DIVISORS(APLL_L_HZ, 12, 2);\n>>> static const struct pll_div apll_b_init_cfg = \n>>> PLL_DIVISORS(APLL_B_HZ, 1, 2);\n>>> #if !defined(CONFIG_TPL_BUILD)\n>>> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, \n>>> 2);\n>>> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, \n>>> 6);\n>>> #endif\n>>> -#endif\n>>>\n>>> static ulong rk3368_clk_get_rate(struct clk *clk);\n>>>\n>>> @@ -85,7 +83,6 @@ static uint32_t rkclk_pll_get_rate(struct \n>>> rk3368_cru *cru,\n>>> }\n>>> }\n>>>\n>>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>>> static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id \n>>> pll_id,\n>>> const struct pll_div *div)\n>>> {\n>>> @@ -125,9 +122,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, \n>>> enum rk3368_pll_id pll_id,\n>>> seamless\n>>> return 0;\n>>> }\n>>> -#endif\n>>>\n>>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>>> static void rkclk_init(struct rk3368_cru *cru)\n>>> {\n>>> u32 apllb, aplll, dpll, cpll, gpll;\n>>> @@ -152,7 +147,7 @@ static void rkclk_init(struct rk3368_cru *cru)\n>>> debug(\"%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\\n\",\n>>> __func__, apllb, aplll, dpll, cpll, gpll);\n>>> }\n>>> -#endif\n>>> +\n>>>\n>>> #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)\n>>> static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)\n>>> @@ -473,9 +468,8 @@ static int rk3368_clk_probe(struct udevice *dev)\n>>>\n>>> priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);\n>>> #endif\n>>> -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)\n>>> +\n>>> rkclk_init(priv->cru);\n>>> -#endif\n>>>\n>>> return 0;\n>>> }\n>>> -- \n>>> 2.7.4\n>>>\n>>>\n>>\n>>\n>>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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