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GET /api/patches/804533/?format=api
{ "id": 804533, "url": "http://patchwork.ozlabs.org/api/patches/804533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-10-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503414919-30820-10-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-08-22T15:15:14", "name": "[U-Boot,09/14] nvme: Apply cache operations on the DMA buffers", "commit_ref": "704e040a51d2456a6c56e79363279b230d37cef7", "pull_url": null, "state": "accepted", "archived": false, "hash": "6c69f9e228076870dd9d59092c8a985db114573c", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-10-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804533/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iBhFFlqT\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcDkG06G1z9sNd\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 01:19:33 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8D114C21F4F; Tue, 22 Aug 2017 15:14:22 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 02B75C21ED4;\n\tTue, 22 Aug 2017 15:12:05 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0C5EAC21E55; Tue, 22 Aug 2017 15:11:15 +0000 (UTC)", "from mail-it0-f68.google.com (mail-it0-f68.google.com\n\t[209.85.214.68])\n\tby lists.denx.de (Postfix) with ESMTPS id 0CC69C21DF3\n\tfor <u-boot@lists.denx.de>; Tue, 22 Aug 2017 15:11:12 +0000 (UTC)", "by mail-it0-f68.google.com with SMTP id w204so3940444ita.5\n\tfor <u-boot@lists.denx.de>; Tue, 22 Aug 2017 08:11:11 -0700 (PDT)", "from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com.\n\t[147.11.156.139]) by smtp.gmail.com with ESMTPSA id\n\ta189sm5182572itd.5.2017.08.22.08.11.08\n\t(version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 22 Aug 2017 08:11:10 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:subject:date:message-id:in-reply-to:references;\n\tbh=DWMyh2Z3PdBkrBnXRlJyo5rCyj5/8EXEM6e66Wkepzg=;\n\tb=iBhFFlqTqy1wllQkUXhjLQ1f7J8LUOO5+WembwLde6J2kmRyhCf4zcWXoRbguc6lHN\n\t+yWdLVoRkh12YkQ2JHpXlGGANATp4of81Q4YZnkch2W1qosX2CQZPYBoDFpPv2BSUME4\n\tyYgNCgGuo4zIztPQsx+8pTHKhpJhE2JXet4FXE3bd87TZynrXFeKHUD0ny7JYmejjW0m\n\tagses9xSGrezrhaEbLpWw8N6pveDb93mE9+zNGyVgcar2V2sPwgoeZGFDy2xn5DB+UpK\n\tS6PcsnjjHY5VZDXdTisgznMZGQvf7qvG2v0oPB32eDBf7R83ycGMJNtDNuYWKr7BXgA4\n\t6H5Q==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=DWMyh2Z3PdBkrBnXRlJyo5rCyj5/8EXEM6e66Wkepzg=;\n\tb=CpmmNEbj6Oc8haiPAr+jCnj3RLv9M+G4LWhD5jeIxn6T7YfSxEA6vKLFCcEZrl3xEK\n\te1IPVfmehyg6oiFxwC0FGRXUi7O56jG8mw5TAobHEYFOCZLQq8djRi/tv3I1a25PkAQr\n\t9hgE2YUDV9bWbbbis5wm3qn7uDNSPBdaELoh9A0KWnEUvVJcUyuLaB/EL5O+NI4PXs44\n\tJJjG2hfJ4bko6acVs2phDfFMSO3tXzrGRpqeesx3+GIvf02o3+DdkyY4ce6sGN/Dmeua\n\ttTn+gGuTSDd/VfjXfUsrcPd2ot4wkRiZbXanY9kf4K0RdcJbWHDIo/Z/CWErDKfd/b7i\n\tH70Q==", "X-Gm-Message-State": "AHYfb5ikBhY9MMdHmR55K5uK8qaMuqDtyByPqp75xEfhUliuAT5PeinD\n\tMT4eQMBX53GaNQ==", "X-Received": "by 10.36.82.5 with SMTP id d5mr298297itb.129.1503414670986;\n\tTue, 22 Aug 2017 08:11:10 -0700 (PDT)", "From": "Bin Meng <bmeng.cn@gmail.com>", "To": "Tom Rini <trini@konsulko.com>, U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Tue, 22 Aug 2017 08:15:14 -0700", "Message-Id": "<1503414919-30820-10-git-send-email-bmeng.cn@gmail.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1503414919-30820-1-git-send-email-bmeng.cn@gmail.com>", "References": "<1503414919-30820-1-git-send-email-bmeng.cn@gmail.com>", "Subject": "[U-Boot] [PATCH 09/14] nvme: Apply cache operations on the DMA\n\tbuffers", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "So far cache operations are only applied on the submission queue and\ncompletion queue, but they are missing in other places like identify\nand block read/write routines.\n\nIn order to correctly operate on the caches, the DMA buffer passed\nto identify routine must be allocated properly on the stack with the\nexisting macro ALLOC_CACHE_ALIGN_BUFFER().\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n---\n\n drivers/nvme/nvme.c | 32 +++++++++++++++++++++++++++++---\n drivers/nvme/nvme_show.c | 7 +++++--\n 2 files changed, 34 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c\nindex c545ce7..67f7d75 100644\n--- a/drivers/nvme/nvme.c\n+++ b/drivers/nvme/nvme.c\n@@ -435,6 +435,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,\n \tu32 page_size = dev->page_size;\n \tint offset = dma_addr & (page_size - 1);\n \tint length = sizeof(struct nvme_id_ctrl);\n+\tint ret;\n \n \tmemset(&c, 0, sizeof(c));\n \tc.identify.opcode = nvme_admin_identify;\n@@ -451,7 +452,12 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,\n \n \tc.identify.cns = cpu_to_le32(cns);\n \n-\treturn nvme_submit_admin_cmd(dev, &c, NULL);\n+\tret = nvme_submit_admin_cmd(dev, &c, NULL);\n+\tif (!ret)\n+\t\tinvalidate_dcache_range(dma_addr,\n+\t\t\t\t\tdma_addr + sizeof(struct nvme_id_ctrl));\n+\n+\treturn ret;\n }\n \n int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,\n@@ -465,6 +471,11 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,\n \tc.features.prp1 = cpu_to_le64(dma_addr);\n \tc.features.fid = cpu_to_le32(fid);\n \n+\t/*\n+\t * TODO: add cache invalidate operation when the size of\n+\t * the DMA buffer is known\n+\t */\n+\n \treturn nvme_submit_admin_cmd(dev, &c, result);\n }\n \n@@ -479,6 +490,11 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,\n \tc.features.fid = cpu_to_le32(fid);\n \tc.features.dword11 = cpu_to_le32(dword11);\n \n+\t/*\n+\t * TODO: add cache flush operation when the size of\n+\t * the DMA buffer is known\n+\t */\n+\n \treturn nvme_submit_admin_cmd(dev, &c, result);\n }\n \n@@ -562,7 +578,8 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)\n \n static int nvme_get_info_from_identify(struct nvme_dev *dev)\n {\n-\tstruct nvme_id_ctrl buf, *ctrl = &buf;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl));\n+\tstruct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf;\n \tint ret;\n \tint shift = NVME_CAP_MPSMIN(dev->cap) + 12;\n \n@@ -627,7 +644,8 @@ static int nvme_blk_probe(struct udevice *udev)\n \tstruct blk_desc *desc = dev_get_uclass_platdata(udev);\n \tstruct nvme_ns *ns = dev_get_priv(udev);\n \tu8 flbas;\n-\tstruct nvme_id_ns buf, *id = &buf;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns));\n+\tstruct nvme_id_ns *id = (struct nvme_id_ns *)buf;\n \tstruct pci_child_platdata *pplat;\n \n \tmemset(ns, 0, sizeof(*ns));\n@@ -672,6 +690,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,\n \tu16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);\n \tu64 total_lbas = blkcnt;\n \n+\tif (!read)\n+\t\tflush_dcache_range((unsigned long)buffer,\n+\t\t\t\t (unsigned long)buffer + total_len);\n+\n \tc.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;\n \tc.rw.flags = 0;\n \tc.rw.nsid = cpu_to_le32(ns->ns_id);\n@@ -706,6 +728,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,\n \t\tbuffer += lbas << ns->lba_shift;\n \t}\n \n+\tif (read)\n+\t\tinvalidate_dcache_range((unsigned long)buffer,\n+\t\t\t\t\t(unsigned long)buffer + total_len);\n+\n \treturn (total_len - temp_len) >> desc->log2blksz;\n }\n \ndiff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c\nindex 5577e5d..5235138 100644\n--- a/drivers/nvme/nvme_show.c\n+++ b/drivers/nvme/nvme_show.c\n@@ -8,6 +8,7 @@\n #include <common.h>\n #include <dm.h>\n #include <errno.h>\n+#include <memalign.h>\n #include <nvme.h>\n #include \"nvme.h\"\n \n@@ -106,8 +107,10 @@ int nvme_print_info(struct udevice *udev)\n {\n \tstruct nvme_ns *ns = dev_get_priv(udev);\n \tstruct nvme_dev *dev = ns->dev;\n-\tstruct nvme_id_ns buf_ns, *id = &buf_ns;\n-\tstruct nvme_id_ctrl buf_ctrl, *ctrl = &buf_ctrl;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns));\n+\tstruct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));\n+\tstruct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;\n \n \tif (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl))\n \t\treturn -EIO;\n", "prefixes": [ "U-Boot", "09/14" ] }