From patchwork Tue Aug 22 15:15:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 804533 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="iBhFFlqT"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xcDkG06G1z9sNd for ; Wed, 23 Aug 2017 01:19:33 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8D114C21F4F; Tue, 22 Aug 2017 15:14:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 02B75C21ED4; Tue, 22 Aug 2017 15:12:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C5EAC21E55; Tue, 22 Aug 2017 15:11:15 +0000 (UTC) Received: from mail-it0-f68.google.com (mail-it0-f68.google.com [209.85.214.68]) by lists.denx.de (Postfix) with ESMTPS id 0CC69C21DF3 for ; Tue, 22 Aug 2017 15:11:12 +0000 (UTC) Received: by mail-it0-f68.google.com with SMTP id w204so3940444ita.5 for ; Tue, 22 Aug 2017 08:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=DWMyh2Z3PdBkrBnXRlJyo5rCyj5/8EXEM6e66Wkepzg=; b=iBhFFlqTqy1wllQkUXhjLQ1f7J8LUOO5+WembwLde6J2kmRyhCf4zcWXoRbguc6lHN +yWdLVoRkh12YkQ2JHpXlGGANATp4of81Q4YZnkch2W1qosX2CQZPYBoDFpPv2BSUME4 yYgNCgGuo4zIztPQsx+8pTHKhpJhE2JXet4FXE3bd87TZynrXFeKHUD0ny7JYmejjW0m agses9xSGrezrhaEbLpWw8N6pveDb93mE9+zNGyVgcar2V2sPwgoeZGFDy2xn5DB+UpK S6PcsnjjHY5VZDXdTisgznMZGQvf7qvG2v0oPB32eDBf7R83ycGMJNtDNuYWKr7BXgA4 6H5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=DWMyh2Z3PdBkrBnXRlJyo5rCyj5/8EXEM6e66Wkepzg=; b=CpmmNEbj6Oc8haiPAr+jCnj3RLv9M+G4LWhD5jeIxn6T7YfSxEA6vKLFCcEZrl3xEK e1IPVfmehyg6oiFxwC0FGRXUi7O56jG8mw5TAobHEYFOCZLQq8djRi/tv3I1a25PkAQr 9hgE2YUDV9bWbbbis5wm3qn7uDNSPBdaELoh9A0KWnEUvVJcUyuLaB/EL5O+NI4PXs44 JJjG2hfJ4bko6acVs2phDfFMSO3tXzrGRpqeesx3+GIvf02o3+DdkyY4ce6sGN/Dmeua tTn+gGuTSDd/VfjXfUsrcPd2ot4wkRiZbXanY9kf4K0RdcJbWHDIo/Z/CWErDKfd/b7i H70Q== X-Gm-Message-State: AHYfb5ikBhY9MMdHmR55K5uK8qaMuqDtyByPqp75xEfhUliuAT5PeinD MT4eQMBX53GaNQ== X-Received: by 10.36.82.5 with SMTP id d5mr298297itb.129.1503414670986; Tue, 22 Aug 2017 08:11:10 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id a189sm5182572itd.5.2017.08.22.08.11.08 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Aug 2017 08:11:10 -0700 (PDT) From: Bin Meng To: Tom Rini , U-Boot Mailing List Date: Tue, 22 Aug 2017 08:15:14 -0700 Message-Id: <1503414919-30820-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1503414919-30820-1-git-send-email-bmeng.cn@gmail.com> References: <1503414919-30820-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 09/14] nvme: Apply cache operations on the DMA buffers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" So far cache operations are only applied on the submission queue and completion queue, but they are missing in other places like identify and block read/write routines. In order to correctly operate on the caches, the DMA buffer passed to identify routine must be allocated properly on the stack with the existing macro ALLOC_CACHE_ALIGN_BUFFER(). Signed-off-by: Bin Meng --- drivers/nvme/nvme.c | 32 +++++++++++++++++++++++++++++--- drivers/nvme/nvme_show.c | 7 +++++-- 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index c545ce7..67f7d75 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -435,6 +435,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, u32 page_size = dev->page_size; int offset = dma_addr & (page_size - 1); int length = sizeof(struct nvme_id_ctrl); + int ret; memset(&c, 0, sizeof(c)); c.identify.opcode = nvme_admin_identify; @@ -451,7 +452,12 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, c.identify.cns = cpu_to_le32(cns); - return nvme_submit_admin_cmd(dev, &c, NULL); + ret = nvme_submit_admin_cmd(dev, &c, NULL); + if (!ret) + invalidate_dcache_range(dma_addr, + dma_addr + sizeof(struct nvme_id_ctrl)); + + return ret; } int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, @@ -465,6 +471,11 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, c.features.prp1 = cpu_to_le64(dma_addr); c.features.fid = cpu_to_le32(fid); + /* + * TODO: add cache invalidate operation when the size of + * the DMA buffer is known + */ + return nvme_submit_admin_cmd(dev, &c, result); } @@ -479,6 +490,11 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, c.features.fid = cpu_to_le32(fid); c.features.dword11 = cpu_to_le32(dword11); + /* + * TODO: add cache flush operation when the size of + * the DMA buffer is known + */ + return nvme_submit_admin_cmd(dev, &c, result); } @@ -562,7 +578,8 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) static int nvme_get_info_from_identify(struct nvme_dev *dev) { - struct nvme_id_ctrl buf, *ctrl = &buf; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl)); + struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf; int ret; int shift = NVME_CAP_MPSMIN(dev->cap) + 12; @@ -627,7 +644,8 @@ static int nvme_blk_probe(struct udevice *udev) struct blk_desc *desc = dev_get_uclass_platdata(udev); struct nvme_ns *ns = dev_get_priv(udev); u8 flbas; - struct nvme_id_ns buf, *id = &buf; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns)); + struct nvme_id_ns *id = (struct nvme_id_ns *)buf; struct pci_child_platdata *pplat; memset(ns, 0, sizeof(*ns)); @@ -672,6 +690,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); u64 total_lbas = blkcnt; + if (!read) + flush_dcache_range((unsigned long)buffer, + (unsigned long)buffer + total_len); + c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write; c.rw.flags = 0; c.rw.nsid = cpu_to_le32(ns->ns_id); @@ -706,6 +728,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, buffer += lbas << ns->lba_shift; } + if (read) + invalidate_dcache_range((unsigned long)buffer, + (unsigned long)buffer + total_len); + return (total_len - temp_len) >> desc->log2blksz; } diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 5577e5d..5235138 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "nvme.h" @@ -106,8 +107,10 @@ int nvme_print_info(struct udevice *udev) { struct nvme_ns *ns = dev_get_priv(udev); struct nvme_dev *dev = ns->dev; - struct nvme_id_ns buf_ns, *id = &buf_ns; - struct nvme_id_ctrl buf_ctrl, *ctrl = &buf_ctrl; + ALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns)); + struct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns; + ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl)); + struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl; if (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl)) return -EIO;