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GET /api/patches/466689/?format=api
{ "id": 466689, "url": "http://patchwork.ozlabs.org/api/patches/466689/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430417955-28252-3-git-send-email-tharvey@gateworks.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1430417955-28252-3-git-send-email-tharvey@gateworks.com>", "list_archive_url": null, "date": "2015-04-30T18:19:14", "name": "[2/3] net: igb: add phy read/write functions that accept phy addr", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "2d08395374de534ca4688729daf77fa4ffa51760", "submitter": { "id": 41730, "url": "http://patchwork.ozlabs.org/api/people/41730/?format=api", "name": "Tim Harvey", "email": "tharvey@gateworks.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430417955-28252-3-git-send-email-tharvey@gateworks.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/466689/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/466689/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (whitealder.osuosl.org\n\t[140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id B688214031A\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 May 2015 04:25:41 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 0E27D91AE8;\n\tThu, 30 Apr 2015 18:25:41 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id jqoix7hLVvEc; Thu, 30 Apr 2015 18:25:39 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 5003591ADE;\n\tThu, 30 Apr 2015 18:25:39 +0000 (UTC)", "from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 6D8181BFA96\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:25:38 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 68923A3581\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:25:38 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id JfiYux2EtOTb for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:25:37 +0000 (UTC)", "from mail-pd0-f169.google.com (mail-pd0-f169.google.com\n\t[209.85.192.169])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 81FEAA3479\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:25:37 +0000 (UTC)", "by pdbqa5 with SMTP id qa5so68351314pdb.1\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 11:25:37 -0700 (PDT)", "from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com.\n\t[68.189.91.139]) by mx.google.com with ESMTPSA id\n\tbs4sm2821374pdb.21.2015.04.30.11.19.21\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 30 Apr 2015 11:19:22 -0700 (PDT)" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "from auto-whitelisted by SQLgrey-1.7.6", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=nnB6tLp8dqD/92ksukXbK1UWF6/uznNlGMDHpM9Rxz0=;\n\tb=YrnfjlfiI8z9uFV0ufCKmUvIZRjgotIM2h4NCxEhuT94D66Nq4HQgJl8yXeHkLoeOJ\n\tduFxycjLjR7U5rc1MwefNRS/CFC4Xueu8fl9jikm1veMQX2e+HL1RRyaYlR8IG+mTQ8G\n\tCy5o5Je/WIzKkyJ/I63kB4JdEO0DOdgKH1RDpJrTfMYdOKN01n4VQx4KFQoa++P+76PT\n\tst02Hk752Se/dD1T0wBX9ecWbWpo59iLhkycjb6byEgf9dd1tGeu+NmrcYWa9UZ6xy4V\n\tah/EnTSTjaeFS0FRg6suqlSiATO0Y+Xk/0i0Yrzeq9cb09v/PYu5AUcMx+JvHCiuB9Lt\n\t381g==", "X-Gm-Message-State": "ALoCoQnQOVp6Q4MPpu31VNMn8eIrH78PhcHjps5PdFeyMfI83io7GY22bNIrrdIZZJsMDfsPPGtj", "X-Received": "by 10.66.177.238 with SMTP id\n\tct14mr10530797pac.121.1430417963171; \n\tThu, 30 Apr 2015 11:19:23 -0700 (PDT)", "From": "Tim Harvey <tharvey@gateworks.com>", "To": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>", "Date": "Thu, 30 Apr 2015 11:19:14 -0700", "Message-Id": "<1430417955-28252-3-git-send-email-tharvey@gateworks.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1430417955-28252-1-git-send-email-tharvey@gateworks.com>", "References": "<1430417955-28252-1-git-send-email-tharvey@gateworks.com>", "Cc": "intel-wired-lan@lists.osuosl.org", "Subject": "[Intel-wired-lan] [PATCH 2/3] net: igb: add phy read/write\n\tfunctions that accept phy addr", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.\nThe existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers\nto this function.\n\nSigned-off-by: Tim Harvey <tharvey@gateworks.com>\n---\n drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +-\n drivers/net/ethernet/intel/igb/e1000_phy.c | 70 ++++++++++++++++++++--------\n drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++-\n 3 files changed, 56 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c\nindex 0f69ef8..d2afd7b 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_82575.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c\n@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)\n \tif (ret_val)\n \t\tgoto out;\n \n-\tret_val = igb_read_phy_reg_mdic(hw, offset, data);\n+\tret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);\n \n \thw->phy.ops.release(hw);\n \n@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)\n \tif (ret_val)\n \t\tgoto out;\n \n-\tret_val = igb_write_phy_reg_mdic(hw, offset, data);\n+\tret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);\n \n \thw->phy.ops.release(hw);\n \ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c\nindex 2307ac6..66c2a09 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c\n@@ -132,9 +132,8 @@ out:\n * Reads the MDI control regsiter in the PHY at offset and stores the\n * information read to data.\n **/\n-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)\n {\n-\tstruct e1000_phy_info *phy = &hw->phy;\n \tu32 i, mdicnfg, mdic = 0;\n \ts32 ret_val = 0;\n \n@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n \tcase e1000_i211:\n \t\tmdicnfg = rd32(E1000_MDICNFG);\n \t\tmdicnfg &= ~(E1000_MDICNFG_PHY_MASK);\n-\t\tmdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);\n+\t\tmdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);\n \t\twr32(E1000_MDICNFG, mdicnfg);\n \t\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n \t\t\t(E1000_MDIC_OP_READ));\n \t\tbreak;\n \tdefault:\n \t\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n-\t\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n+\t\t\t(addr << E1000_MDIC_PHY_SHIFT) |\n \t\t\t(E1000_MDIC_OP_READ));\n \t\tbreak;\n \t}\n@@ -214,9 +213,8 @@ out:\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\n-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)\n {\n-\tstruct e1000_phy_info *phy = &hw->phy;\n \tu32 i, mdicnfg, mdic = 0;\n \ts32 ret_val = 0;\n \n@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)\n \t\tgoto out;\n \n \tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n-\t\tret_val = igb_write_phy_reg_mdic(hw,\n+\t\tret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,\n \t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n \t\t\t\t\t\t (u16)offset);\n \t\tif (ret_val) {\n@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)\n \t\t}\n \t}\n \n-\tret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n-\t\t\t\t\tdata);\n+\tret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,\n+\t\t\t\t\tMAX_PHY_REG_ADDRESS & offset, data);\n \n \thw->phy.ops.release(hw);\n \n@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)\n \t\tgoto out;\n \n \tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n-\t\tret_val = igb_write_phy_reg_mdic(hw,\n+\t\tret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,\n \t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n \t\t\t\t\t\t (u16)offset);\n \t\tif (ret_val) {\n@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)\n \t\t}\n \t}\n \n-\tret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n-\t\t\t\t\t data);\n+\tret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,\n+\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset, data);\n \n \thw->phy.ops.release(hw);\n \n@@ -2464,8 +2462,9 @@ out:\n }\n \n /**\n- * igb_write_phy_reg_gs40g - Write GS40G PHY register\n+ * igb_write_reg_gs40g - Write GS40G PHY register\n * @hw: pointer to the HW structure\n+ * @addr: phy address to write to\n * @offset: lower half is register offset to write to\n * upper half is page to use.\n * @data: data to write at register offset\n@@ -2473,7 +2472,7 @@ out:\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\n-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)\n {\n \ts32 ret_val;\n \tu16 page = offset >> GS40G_PAGE_SHIFT;\n@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n \tif (ret_val)\n \t\treturn ret_val;\n \n-\tret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n+\tret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);\n \tif (ret_val)\n \t\tgoto release;\n-\tret_val = igb_write_phy_reg_mdic(hw, offset, data);\n+\tret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);\n \n release:\n \thw->phy.ops.release(hw);\n@@ -2494,8 +2493,24 @@ release:\n }\n \n /**\n- * igb_read_phy_reg_gs40g - Read GS40G PHY register\n+ * igb_write_phy_reg_gs40g - Write GS40G PHY register\n+ * @hw: pointer to the HW structure\n+ * @offset: lower half is register offset to write to\n+ * upper half is page to use.\n+ * @data: data to write at register offset\n+ *\n+ * Acquires semaphore, if necessary, then writes the data to PHY register\n+ * at the offset. Release any acquired semaphores before exiting.\n+ **/\n+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n+{\n+\treturn igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);\n+}\n+\n+/**\n+ * igb_read_reg_gs40g - Read GS40G PHY register\n * @hw: pointer to the HW structure\n+ * @addr: phy address to read from\n * @offset: lower half is register offset to read to\n * upper half is page to use.\n * @data: data to read at register offset\n@@ -2503,7 +2518,7 @@ release:\n * Acquires semaphore, if necessary, then reads the data in the PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\n-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)\n {\n \ts32 ret_val;\n \tu16 page = offset >> GS40G_PAGE_SHIFT;\n@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n \tif (ret_val)\n \t\treturn ret_val;\n \n-\tret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n+\tret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);\n \tif (ret_val)\n \t\tgoto release;\n-\tret_val = igb_read_phy_reg_mdic(hw, offset, data);\n+\tret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);\n \n release:\n \thw->phy.ops.release(hw);\n@@ -2524,6 +2539,21 @@ release:\n }\n \n /**\n+ * igb_read_phy_reg_gs40g - Read GS40G PHY register\n+ * @hw: pointer to the HW structure\n+ * @offset: lower half is register offset to read to\n+ * upper half is page to use.\n+ * @data: data to read at register offset\n+ *\n+ * Acquires semaphore, if necessary, then reads the data in the PHY register\n+ * at the offset. Release any acquired semaphores before exiting.\n+ **/\n+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n+{\n+\treturn igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);\n+}\n+\n+/**\n * igb_set_master_slave_mode - Setup PHY for Master/slave mode\n * @hw: pointer to the HW structure\n *\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h\nindex 7af4ffa..6256e76 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.h\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h\n@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,\n void igb_power_up_phy_copper(struct e1000_hw *hw);\n void igb_power_down_phy_copper(struct e1000_hw *hw);\n s32 igb_phy_init_script_igp3(struct e1000_hw *hw);\n-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);\n-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);\n+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);\n+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);\n s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);\n s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);\n s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);\n@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);\n s32 igb_get_cable_length_82580(struct e1000_hw *hw);\n s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);\n s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);\n+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);\n+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);\n s32 igb_check_polarity_m88(struct e1000_hw *hw);\n \n /* IGP01E1000 Specific Registers */\n", "prefixes": [ "2/3" ] }