From patchwork Thu Apr 30 18:19:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 466689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ozlabs.org (Postfix) with ESMTP id B688214031A for ; Fri, 1 May 2015 04:25:41 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 0E27D91AE8; Thu, 30 Apr 2015 18:25:41 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jqoix7hLVvEc; Thu, 30 Apr 2015 18:25:39 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 5003591ADE; Thu, 30 Apr 2015 18:25:39 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137]) by ash.osuosl.org (Postfix) with ESMTP id 6D8181BFA96 for ; Thu, 30 Apr 2015 18:25:38 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 68923A3581 for ; Thu, 30 Apr 2015 18:25:38 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JfiYux2EtOTb for ; Thu, 30 Apr 2015 18:25:37 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by fraxinus.osuosl.org (Postfix) with ESMTPS id 81FEAA3479 for ; Thu, 30 Apr 2015 18:25:37 +0000 (UTC) Received: by pdbqa5 with SMTP id qa5so68351314pdb.1 for ; Thu, 30 Apr 2015 11:25:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nnB6tLp8dqD/92ksukXbK1UWF6/uznNlGMDHpM9Rxz0=; b=YrnfjlfiI8z9uFV0ufCKmUvIZRjgotIM2h4NCxEhuT94D66Nq4HQgJl8yXeHkLoeOJ duFxycjLjR7U5rc1MwefNRS/CFC4Xueu8fl9jikm1veMQX2e+HL1RRyaYlR8IG+mTQ8G Cy5o5Je/WIzKkyJ/I63kB4JdEO0DOdgKH1RDpJrTfMYdOKN01n4VQx4KFQoa++P+76PT st02Hk752Se/dD1T0wBX9ecWbWpo59iLhkycjb6byEgf9dd1tGeu+NmrcYWa9UZ6xy4V ah/EnTSTjaeFS0FRg6suqlSiATO0Y+Xk/0i0Yrzeq9cb09v/PYu5AUcMx+JvHCiuB9Lt 381g== X-Gm-Message-State: ALoCoQnQOVp6Q4MPpu31VNMn8eIrH78PhcHjps5PdFeyMfI83io7GY22bNIrrdIZZJsMDfsPPGtj X-Received: by 10.66.177.238 with SMTP id ct14mr10530797pac.121.1430417963171; Thu, 30 Apr 2015 11:19:23 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id bs4sm2821374pdb.21.2015.04.30.11.19.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 11:19:22 -0700 (PDT) From: Tim Harvey To: Jeff Kirsher Date: Thu, 30 Apr 2015 11:19:14 -0700 Message-Id: <1430417955-28252-3-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> References: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> Cc: intel-wired-lan@lists.osuosl.org Subject: [Intel-wired-lan] [PATCH 2/3] net: igb: add phy read/write functions that accept phy addr X-BeenThere: intel-wired-lan@lists.osuosl.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@lists.osuosl.org Sender: "Intel-wired-lan" Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers to this function. Signed-off-by: Tim Harvey --- drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +- drivers/net/ethernet/intel/igb/e1000_phy.c | 70 ++++++++++++++++++++-------- drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++- 3 files changed, 56 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c index 0f69ef8..d2afd7b 100644 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c @@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) if (ret_val) goto out; - ret_val = igb_read_phy_reg_mdic(hw, offset, data); + ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); hw->phy.ops.release(hw); @@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) if (ret_val) goto out; - ret_val = igb_write_phy_reg_mdic(hw, offset, data); + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); hw->phy.ops.release(hw); diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c index 2307ac6..66c2a09 100644 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c @@ -132,9 +132,8 @@ out: * Reads the MDI control regsiter in the PHY at offset and stores the * information read to data. **/ -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) { - struct e1000_phy_info *phy = &hw->phy; u32 i, mdicnfg, mdic = 0; s32 ret_val = 0; @@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) case e1000_i211: mdicnfg = rd32(E1000_MDICNFG); mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); - mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); + mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); wr32(E1000_MDICNFG, mdicnfg); mdic = ((offset << E1000_MDIC_REG_SHIFT) | (E1000_MDIC_OP_READ)); break; default: mdic = ((offset << E1000_MDIC_REG_SHIFT) | - (phy->addr << E1000_MDIC_PHY_SHIFT) | + (addr << E1000_MDIC_PHY_SHIFT) | (E1000_MDIC_OP_READ)); break; } @@ -214,9 +213,8 @@ out: * * Writes data to MDI control register in the PHY at offset. **/ -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) { - struct e1000_phy_info *phy = &hw->phy; u32 i, mdicnfg, mdic = 0; s32 ret_val = 0; @@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) goto out; if (offset > MAX_PHY_MULTI_PAGE_REG) { - ret_val = igb_write_phy_reg_mdic(hw, + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, IGP01E1000_PHY_PAGE_SELECT, (u16)offset); if (ret_val) { @@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) } } - ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, - data); + ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, + MAX_PHY_REG_ADDRESS & offset, data); hw->phy.ops.release(hw); @@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) goto out; if (offset > MAX_PHY_MULTI_PAGE_REG) { - ret_val = igb_write_phy_reg_mdic(hw, + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, IGP01E1000_PHY_PAGE_SELECT, (u16)offset); if (ret_val) { @@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) } } - ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, - data); + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, + MAX_PHY_REG_ADDRESS & offset, data); hw->phy.ops.release(hw); @@ -2464,8 +2462,9 @@ out: } /** - * igb_write_phy_reg_gs40g - Write GS40G PHY register + * igb_write_reg_gs40g - Write GS40G PHY register * @hw: pointer to the HW structure + * @addr: phy address to write to * @offset: lower half is register offset to write to * upper half is page to use. * @data: data to write at register offset @@ -2473,7 +2472,7 @@ out: * Acquires semaphore, if necessary, then writes the data to PHY register * at the offset. Release any acquired semaphores before exiting. **/ -s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) { s32 ret_val; u16 page = offset >> GS40G_PAGE_SHIFT; @@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) if (ret_val) return ret_val; - ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); + ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); if (ret_val) goto release; - ret_val = igb_write_phy_reg_mdic(hw, offset, data); + ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); release: hw->phy.ops.release(hw); @@ -2494,8 +2493,24 @@ release: } /** - * igb_read_phy_reg_gs40g - Read GS40G PHY register + * igb_write_phy_reg_gs40g - Write GS40G PHY register + * @hw: pointer to the HW structure + * @offset: lower half is register offset to write to + * upper half is page to use. + * @data: data to write at register offset + * + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) +{ + return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); +} + +/** + * igb_read_reg_gs40g - Read GS40G PHY register * @hw: pointer to the HW structure + * @addr: phy address to read from * @offset: lower half is register offset to read to * upper half is page to use. * @data: data to read at register offset @@ -2503,7 +2518,7 @@ release: * Acquires semaphore, if necessary, then reads the data in the PHY register * at the offset. Release any acquired semaphores before exiting. **/ -s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) { s32 ret_val; u16 page = offset >> GS40G_PAGE_SHIFT; @@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) if (ret_val) return ret_val; - ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); + ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); if (ret_val) goto release; - ret_val = igb_read_phy_reg_mdic(hw, offset, data); + ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); release: hw->phy.ops.release(hw); @@ -2524,6 +2539,21 @@ release: } /** + * igb_read_phy_reg_gs40g - Read GS40G PHY register + * @hw: pointer to the HW structure + * @offset: lower half is register offset to read to + * upper half is page to use. + * @data: data to read at register offset + * + * Acquires semaphore, if necessary, then reads the data in the PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) +{ + return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); +} + +/** * igb_set_master_slave_mode - Setup PHY for Master/slave mode * @hw: pointer to the HW structure * diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h index 7af4ffa..6256e76 100644 --- a/drivers/net/ethernet/intel/igb/e1000_phy.h +++ b/drivers/net/ethernet/intel/igb/e1000_phy.h @@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, void igb_power_up_phy_copper(struct e1000_hw *hw); void igb_power_down_phy_copper(struct e1000_hw *hw); s32 igb_phy_init_script_igp3(struct e1000_hw *hw); -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); @@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); s32 igb_get_cable_length_82580(struct e1000_hw *hw); s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); s32 igb_check_polarity_m88(struct e1000_hw *hw); /* IGP01E1000 Specific Registers */