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GET /api/patches/366309/?format=api
{ "id": 366309, "url": "http://patchwork.ozlabs.org/api/patches/366309/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1404291772-2644-6-git-send-email-jingchang.lu@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1404291772-2644-6-git-send-email-jingchang.lu@freescale.com>", "list_archive_url": null, "date": "2014-07-02T09:02:52", "name": "[5/5] ARM: imx: Add Freescale LS1021A SMP support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d8785cd463b85551f67bc026865a06fc03e1fedd", "submitter": { "id": 46273, "url": "http://patchwork.ozlabs.org/api/people/46273/?format=api", "name": "Jingchang Lu", "email": "jingchang.lu@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1404291772-2644-6-git-send-email-jingchang.lu@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/366309/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/366309/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 9A7211400E1\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tWed, 2 Jul 2014 19:52:05 +1000 (EST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1X2H9h-0005hB-5A; Wed, 02 Jul 2014 09:48:45 +0000", "from mail-bn1blp0182.outbound.protection.outlook.com\n\t([207.46.163.182] helo=na01-bn1-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1X2H9d-0005a1-0g\n\tfor linux-arm-kernel@lists.infradead.org;\n\tWed, 02 Jul 2014 09:48:42 +0000", "from BL2PR03MB467.namprd03.prod.outlook.com (10.141.92.23) by\n\tBL2PR03MB307.namprd03.prod.outlook.com (10.141.68.21) with Microsoft\n\tSMTP Server (TLS) id 15.0.974.11; Wed, 2 Jul 2014 09:48:18 +0000", "from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by\n\tBL2PR03MB467.namprd03.prod.outlook.com (10.141.92.23) with Microsoft\n\tSMTP Server (TLS) id 15.0.974.11; Wed, 2 Jul 2014 09:48:09 +0000", "from BN1BFFO11FD046.protection.gbl (10.255.156.132) by\n\tCH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft\n\tSMTP Server (TLS) id 15.0.974.11 via Frontend Transport;\n\tWed, 2 Jul 2014 09:48:08 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1BFFO11FD046.mail.protection.outlook.com (10.58.145.1) with\n\tMicrosoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport;\n\tWed, 2 Jul 2014 09:48:08 +0000", "from rock.ap.freescale.net (rock.ap.freescale.net [10.193.20.106])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts629lmLI017458; Wed, 2 Jul 2014 02:48:06 -0700" ], "From": "Jingchang Lu <jingchang.lu@freescale.com>", "To": "<shawn.guo@linaro.org>", "Subject": "[PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support", "Date": "Wed, 2 Jul 2014 17:02:52 +0800", "Message-ID": "<1404291772-2644-6-git-send-email-jingchang.lu@freescale.com>", "X-Mailer": "git-send-email 1.8.0", "In-Reply-To": "<1404291772-2644-1-git-send-email-jingchang.lu@freescale.com>", "References": "<1404291772-2644-1-git-send-email-jingchang.lu@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(6009001)(199002)(189002)(87286001)(81156004)(19580405001)(68736004)(50226001)(105606002)(19580395003)(87936001)(76482001)(81542001)(81342001)(2351001)(44976005)(104166001)(20776003)(21056001)(80022001)(102836001)(84676001)(6806004)(107046002)(69596002)(83322001)(92726001)(106466001)(26826002)(89996001)(77156001)(86362001)(36756003)(93916002)(79102001)(77982001)(99396002)(85852003)(85306003)(48376002)(46102001)(31966008)(47776003)(104016002)(64706001)(88136002)(97736001)(62966002)(74502001)(50466002)(83072002)(74662001)(50986999)(95666004)(76176999)(92566001)(4396001)(33646001)(229853001);\n\tDIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB467; H:az84smr01.freescale.net;\n\tFPR:; \n\tMLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "BCL:0;PCL:0;RULEID:", "BCL:0;PCL:0;RULEID:" ], "X-Forefront-PRVS": "0260457E99", "Received-SPF": "Fail (: domain of freescale.com does not designate 192.88.158.2\n\tas permitted sender) receiver=; client-ip=192.88.158.2;\n\thelo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=jingchang.lu@freescale.com; ", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20140702_024841_219929_5E6FD3F5 ", "X-CRM114-Status": "GOOD ( 10.76 )", "X-Spam-Score": "-0.7 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[207.46.163.182 listed in wl.mailspike.net]\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [207.46.163.182 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record", "Cc": "mark.rutland@arm.com, devicetree@vger.kernel.org,\n\tJingchang Lu <b35083@freescale.com>, linux-arm-kernel@lists.infradead.org", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "From: Jingchang Lu <b35083@freescale.com>\n\nFreescale LS1021A SoC deploys two cortex-A7 processors,\nthis adds bring-up support for the secondary core.\n\nSigned-off-by: Jingchang Lu <b35083@freescale.com>\n---\n arch/arm/mach-imx/common.h | 2 ++\n arch/arm/mach-imx/headsmp.S | 11 ++++++++++\n arch/arm/mach-imx/mach-ls1021a.c | 1 +\n arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 58 insertions(+)", "diff": "diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h\nindex e0632d1..8cdd498 100644\n--- a/arch/arm/mach-imx/common.h\n+++ b/arch/arm/mach-imx/common.h\n@@ -98,6 +98,7 @@ void v7_secondary_startup(void);\n void imx_scu_map_io(void);\n void imx_smp_prepare(void);\n void imx_scu_standby_enable(void);\n+void ls1021a_secondary_startup(void);\n #else\n static inline void imx_scu_map_io(void) {}\n static inline void imx_smp_prepare(void) {}\n@@ -158,5 +159,6 @@ static inline void imx_init_l2cache(void) {}\n #endif\n \n extern struct smp_operations imx_smp_ops;\n+extern struct smp_operations ls1021a_smp_ops;\n \n #endif\ndiff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S\nindex de5047c..fdd93d9 100644\n--- a/arch/arm/mach-imx/headsmp.S\n+++ b/arch/arm/mach-imx/headsmp.S\n@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup)\n \tset_diag_reg\n \tb\tsecondary_startup\n ENDPROC(v7_secondary_startup)\n+\n+ENTRY(ls1021a_secondary_startup)\n+\t/* set CNTFREQ of secondary core */\n+\tldr\tr0, =12500000\n+\tmcr \tp15, 0, r0, c14, c0, 0\n+\t/* disable Physical and Virtural Timer */\n+\tmov\tr0, #0x0\n+\tmcr\tp15, 0, r0, c14, c2, 1\n+\tmcr\tp15, 0, r0, c14, c3, 1\n+\tb\tsecondary_startup\n+ENDPROC(ls1021a_secondary_startup)\ndiff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c\nindex d1a9bb9..9931c5b 100644\n--- a/arch/arm/mach-imx/mach-ls1021a.c\n+++ b/arch/arm/mach-imx/mach-ls1021a.c\n@@ -43,6 +43,7 @@ DT_MACHINE_START(LS1021A, \"Freescale LS1021A\")\n #ifdef CONFIG_ZONE_DMA\n \t.dma_zone_size\t= SZ_128M,\n #endif\n+\t.smp\t\t= smp_ops(ls1021a_smp_ops),\n \t.init_machine = ls1021a_init_machine,\n \t.dt_compat\t= ls1021a_dt_compat,\n \t.restart\t= mxc_restart,\ndiff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c\nindex 5b57c17..8e1bcce 100644\n--- a/arch/arm/mach-imx/platsmp.c\n+++ b/arch/arm/mach-imx/platsmp.c\n@@ -16,6 +16,8 @@\n #include <asm/page.h>\n #include <asm/smp_scu.h>\n #include <asm/mach/map.h>\n+#include <linux/of.h>\n+#include <linux/of_address.h>\n \n #include \"common.h\"\n #include \"hardware.h\"\n@@ -104,3 +106,45 @@ struct smp_operations imx_smp_ops __initdata = {\n \t.cpu_kill\t\t= imx_cpu_kill,\n #endif\n };\n+\n+static void __iomem *dcfg_base;\n+#define DCFG_CCSR_BRR\t\t0xE4\n+#define DCFG_CCSR_SCRATCHRW1\t0x200\n+\n+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)\n+{\n+\tunsigned long paddr;\n+\n+\tpaddr = virt_to_phys(ls1021a_secondary_startup);\n+\twritel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\t/* release core for booting */\n+\twritel_relaxed(cpu_to_be32(0x1 << cpu), dcfg_base + DCFG_CCSR_BRR);\n+\n+\treturn 0;\n+}\n+\n+static void __init ls1021a_smp_init_cpus(void)\n+{\n+\tint i, ncores;\n+\t/* get number of cores from CP15 L2 controller register(L2CTLR)*/\n+\tasm volatile (\"mrc p15, 1, %0, c9, c0, 2\" : \"=r\" (ncores));\n+\n+\tncores = ((ncores >> 24) & 0x3) + 1;\n+\tfor (i = ncores; i < NR_CPUS; i++)\n+\t\tset_cpu_possible(i, false);\n+}\n+\n+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)\n+{\n+\tstruct device_node *np;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n+\tdcfg_base = of_iomap(np, 0);\n+\tWARN_ON(!dcfg_base);\n+}\n+\n+struct smp_operations ls1021a_smp_ops __initdata = {\n+\t.smp_init_cpus\t\t= ls1021a_smp_init_cpus,\n+\t.smp_prepare_cpus\t= ls1021a_smp_prepare_cpus,\n+\t.smp_boot_secondary\t= ls1021a_boot_secondary,\n+};\n", "prefixes": [ "5/5" ] }