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Wed, 2 Jul 2014 02:48:06 -0700 From: Jingchang Lu To: Subject: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP support Date: Wed, 2 Jul 2014 17:02:52 +0800 Message-ID: <1404291772-2644-6-git-send-email-jingchang.lu@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1404291772-2644-1-git-send-email-jingchang.lu@freescale.com> References: <1404291772-2644-1-git-send-email-jingchang.lu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199002)(189002)(87286001)(81156004)(19580405001)(68736004)(50226001)(105606002)(19580395003)(87936001)(76482001)(81542001)(81342001)(2351001)(44976005)(104166001)(20776003)(21056001)(80022001)(102836001)(84676001)(6806004)(107046002)(69596002)(83322001)(92726001)(106466001)(26826002)(89996001)(77156001)(86362001)(36756003)(93916002)(79102001)(77982001)(99396002)(85852003)(85306003)(48376002)(46102001)(31966008)(47776003)(104016002)(64706001)(88136002)(97736001)(62966002)(74502001)(50466002)(83072002)(74662001)(50986999)(95666004)(76176999)(92566001)(4396001)(33646001)(229853001); DIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB467; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 0260457E99 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=jingchang.lu@freescale.com; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140702_024841_219929_5E6FD3F5 X-CRM114-Status: GOOD ( 10.76 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [207.46.163.182 listed in wl.mailspike.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [207.46.163.182 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Jingchang Lu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Jingchang Lu Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Jingchang Lu --- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/headsmp.S | 11 ++++++++++ arch/arm/mach-imx/mach-ls1021a.c | 1 + arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index e0632d1..8cdd498 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -98,6 +98,7 @@ void v7_secondary_startup(void); void imx_scu_map_io(void); void imx_smp_prepare(void); void imx_scu_standby_enable(void); +void ls1021a_secondary_startup(void); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} @@ -158,5 +159,6 @@ static inline void imx_init_l2cache(void) {} #endif extern struct smp_operations imx_smp_ops; +extern struct smp_operations ls1021a_smp_ops; #endif diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index de5047c..fdd93d9 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup) set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) + +ENTRY(ls1021a_secondary_startup) + /* set CNTFREQ of secondary core */ + ldr r0, =12500000 + mcr p15, 0, r0, c14, c0, 0 + /* disable Physical and Virtural Timer */ + mov r0, #0x0 + mcr p15, 0, r0, c14, c2, 1 + mcr p15, 0, r0, c14, c3, 1 + b secondary_startup +ENDPROC(ls1021a_secondary_startup) diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c index d1a9bb9..9931c5b 100644 --- a/arch/arm/mach-imx/mach-ls1021a.c +++ b/arch/arm/mach-imx/mach-ls1021a.c @@ -43,6 +43,7 @@ DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_128M, #endif + .smp = smp_ops(ls1021a_smp_ops), .init_machine = ls1021a_init_machine, .dt_compat = ls1021a_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 5b57c17..8e1bcce 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "common.h" #include "hardware.h" @@ -104,3 +106,45 @@ struct smp_operations imx_smp_ops __initdata = { .cpu_kill = imx_cpu_kill, #endif }; + +static void __iomem *dcfg_base; +#define DCFG_CCSR_BRR 0xE4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + +static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long paddr; + + paddr = virt_to_phys(ls1021a_secondary_startup); + writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1); + /* release core for booting */ + writel_relaxed(cpu_to_be32(0x1 << cpu), dcfg_base + DCFG_CCSR_BRR); + + return 0; +} + +static void __init ls1021a_smp_init_cpus(void) +{ + int i, ncores; + /* get number of cores from CP15 L2 controller register(L2CTLR)*/ + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores)); + + ncores = ((ncores >> 24) & 0x3) + 1; + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +} + +static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg"); + dcfg_base = of_iomap(np, 0); + WARN_ON(!dcfg_base); +} + +struct smp_operations ls1021a_smp_ops __initdata = { + .smp_init_cpus = ls1021a_smp_init_cpus, + .smp_prepare_cpus = ls1021a_smp_prepare_cpus, + .smp_boot_secondary = ls1021a_boot_secondary, +};