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{
    "id": 354082,
    "url": "http://patchwork.ozlabs.org/api/patches/354082/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-11-git-send-email-hdoyu@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1401448834-32659-11-git-send-email-hdoyu@nvidia.com>",
    "list_archive_url": null,
    "date": "2014-05-30T11:20:23",
    "name": "[PATCHv8,10/21] iommu/tegra: smmu: allow duplicate ASID wirte",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "5afb9a9d46a73556e0e2e7afb2331b4d2575f9e1",
    "submitter": {
        "id": 10265,
        "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api",
        "name": "Hiroshi Doyu",
        "email": "hdoyu@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-11-git-send-email-hdoyu@nvidia.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/354082/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/354082/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 6B0CF1400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:50 +1000 (EST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754458AbaE3LUr (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:47 -0400",
            "from hqemgate15.nvidia.com ([216.228.121.64]:17137 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753146AbaE3LUp (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:45 -0400",
            "from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid <B538869820001>; Fri, 30 May 2014 04:20:34 -0700",
            "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp08.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:15:41 -0700",
            "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:44 -0700",
            "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:41 +0200"
        ],
        "X-PGP-Universal": "processed;\n\tby hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:41 -0700",
        "From": "Hiroshi Doyu <hdoyu@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "Subject": "[PATCHv8 10/21] iommu/tegra: smmu: allow duplicate ASID wirte",
        "Date": "Fri, 30 May 2014 14:20:23 +0300",
        "Message-ID": "<1401448834-32659-11-git-send-email-hdoyu@nvidia.com>",
        "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f",
        "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "The device, which belongs to the same ASID, can try to enable the same\nASID as the other swgroup devices. This should be allowed but just\nskip the actual register write. If the write value is different, it\nwill return -EINVAL.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\n---\n drivers/iommu/tegra-smmu.c | 20 ++++++++------------\n 1 file changed, 8 insertions(+), 12 deletions(-)",
    "diff": "diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c\nindex 1d3f695d3c66..caa531cb1c50 100644\n--- a/drivers/iommu/tegra-smmu.c\n+++ b/drivers/iommu/tegra-smmu.c\n@@ -417,9 +417,13 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,\n \t\toffs = HWGRP_ASID_REG(i);\n \t\tval = smmu_read(smmu, offs);\n \t\tif (on) {\n-\t\t\tif (WARN_ON(val & mask))\n-\t\t\t\tgoto err_hw_busy;\n-\t\t\tval |= mask;\n+\t\t\tif (val) {\n+\t\t\t\tif (WARN_ON(val != mask))\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\tgoto skip;\n+\t\t\t}\n+\n+\t\t\tval = mask;\n \t\t\tmemcpy(c->hwgrp, map, sizeof(u64));\n \t\t} else {\n \t\t\tWARN_ON((val & mask) == mask);\n@@ -429,16 +433,8 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c,\n \t}\n \n \tFLUSH_SMMU_REGS(smmu);\n+skip:\n \treturn 0;\n-\n-err_hw_busy:\n-\tfor_each_set_bit(i, map, TEGRA_SWGROUP_MAX) {\n-\t\toffs = HWGRP_ASID_REG(i);\n-\t\tval = smmu_read(smmu, offs);\n-\t\tval &= ~mask;\n-\t\tsmmu_write(smmu, val, offs);\n-\t}\n-\treturn -EBUSY;\n }\n \n static int smmu_client_set_hwgrp(struct smmu_client *c,\n",
    "prefixes": [
        "PATCHv8",
        "10/21"
    ]
}