From patchwork Fri May 30 11:20:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 354082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6B0CF1400E2 for ; Fri, 30 May 2014 21:20:50 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754458AbaE3LUr (ORCPT ); Fri, 30 May 2014 07:20:47 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17137 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753146AbaE3LUp (ORCPT ); Fri, 30 May 2014 07:20:45 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 30 May 2014 04:20:34 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 30 May 2014 04:15:41 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:41 -0700 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 04:20:44 -0700 Received: from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com (10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 13:20:41 +0200 From: Hiroshi Doyu To: Subject: [PATCHv8 10/21] iommu/tegra: smmu: allow duplicate ASID wirte Date: Fri, 30 May 2014 14:20:23 +0300 Message-ID: <1401448834-32659-11-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 2.0.0.rc1.15.g7e76a2f In-Reply-To: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> References: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The device, which belongs to the same ASID, can try to enable the same ASID as the other swgroup devices. This should be allowed but just skip the actual register write. If the write value is different, it will return -EINVAL. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1d3f695d3c66..caa531cb1c50 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -417,9 +417,13 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, offs = HWGRP_ASID_REG(i); val = smmu_read(smmu, offs); if (on) { - if (WARN_ON(val & mask)) - goto err_hw_busy; - val |= mask; + if (val) { + if (WARN_ON(val != mask)) + return -EINVAL; + goto skip; + } + + val = mask; memcpy(c->hwgrp, map, sizeof(u64)); } else { WARN_ON((val & mask) == mask); @@ -429,16 +433,8 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, } FLUSH_SMMU_REGS(smmu); +skip: return 0; - -err_hw_busy: - for_each_set_bit(i, map, TEGRA_SWGROUP_MAX) { - offs = HWGRP_ASID_REG(i); - val = smmu_read(smmu, offs); - val &= ~mask; - smmu_write(smmu, val, offs); - } - return -EBUSY; } static int smmu_client_set_hwgrp(struct smmu_client *c,