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GET /api/patches/354078/?format=api
{ "id": 354078, "url": "http://patchwork.ozlabs.org/api/patches/354078/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-7-git-send-email-hdoyu@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1401448834-32659-7-git-send-email-hdoyu@nvidia.com>", "list_archive_url": null, "date": "2014-05-30T11:20:19", "name": "[PATCHv8,06/21] ARM: tegra: create a DT header defining SWGROUP ID", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "617c8c57d0b6d3f99e98bba096be126929d357fd", "submitter": { "id": 10265, "url": "http://patchwork.ozlabs.org/api/people/10265/?format=api", "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1401448834-32659-7-git-send-email-hdoyu@nvidia.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/354078/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/354078/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-tegra-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 10B181400E2\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 30 May 2014 21:20:48 +1000 (EST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752368AbaE3LUp (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 30 May 2014 07:20:45 -0400", "from hqemgate16.nvidia.com ([216.228.121.65]:3680 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752220AbaE3LUn (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tFri, 30 May 2014 07:20:43 -0400", "from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid <B538869810000>; Fri, 30 May 2014 04:20:33 -0700", "from hqemhub01.nvidia.com ([172.20.12.94])\n\tby hqnvupgp07.nvidia.com (PGP Universal service);\n\tFri, 30 May 2014 04:13:30 -0700", "from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com\n\t(172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 04:20:43 -0700", "from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com\n\t(10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0;\n\tFri, 30 May 2014 13:20:40 +0200" ], "X-PGP-Universal": "processed;\n\tby hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:30 -0700", "From": "Hiroshi Doyu <hdoyu@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "Subject": "[PATCHv8 06/21] ARM: tegra: create a DT header defining SWGROUP ID", "Date": "Fri, 30 May 2014 14:20:19 +0300", "Message-ID": "<1401448834-32659-7-git-send-email-hdoyu@nvidia.com>", "X-Mailer": "git-send-email 2.0.0.rc1.15.g7e76a2f", "In-Reply-To": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "References": "<1401448834-32659-1-git-send-email-hdoyu@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-tegra-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-tegra.vger.kernel.org>", "X-Mailing-List": "linux-tegra@vger.kernel.org" }, "content": "Create a header file to define the swgroup IDs used by the IOMMU(SMMU)\nbinding. \"swgroup\" is a group of H/W clients which a Tegra SoC\nsupports. This unique ID can be used to calculate MC_SMMU_<swgroup\nname>_ASID_0 register offset and MC_<swgroup name>_HOTRESET_*_0\nregister bit. This will allow the same header to be used by both\ndevice tree files, and drivers implementing this binding, which\nguarantees that the two stay in sync. This also makes device trees\nmore readable by using names instead of magic numbers. For HOTRESET\nbit shifting we need another conversion table, which will come later.\n\nSigned-off-by: Hiroshi Doyu <hdoyu@nvidia.com>\nCc: Mark Zhang <markz@nvidia.com>\n---\n include/dt-bindings/memory/tegra-swgroup.h | 50 ++++++++++++++++++++++++++++++\n 1 file changed, 50 insertions(+)\n create mode 100644 include/dt-bindings/memory/tegra-swgroup.h", "diff": "diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h\nnew file mode 100644\nindex 000000000000..32dd307e5f8e\n--- /dev/null\n+++ b/include/dt-bindings/memory/tegra-swgroup.h\n@@ -0,0 +1,50 @@\n+/*\n+ * This header provides constants for binding nvidia,swgroup ID\n+ */\n+\n+#ifndef _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H\n+#define _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H\n+\n+#define TEGRA_SWGROUP_AFI\t0\t/* 0x238 */\n+#define TEGRA_SWGROUP_AVPC\t1\t/* 0x23c */\n+#define TEGRA_SWGROUP_DC\t2\t/* 0x240 */\n+#define TEGRA_SWGROUP_DCB\t3\t/* 0x244 */\n+#define TEGRA_SWGROUP_EPP\t4\t/* 0x248 */\n+#define TEGRA_SWGROUP_G2\t5\t/* 0x24c */\n+#define TEGRA_SWGROUP_HC\t6\t/* 0x250 */\n+#define TEGRA_SWGROUP_HDA\t7\t/* 0x254 */\n+#define TEGRA_SWGROUP_ISP\t8\t/* 0x258 */\n+#define TEGRA_SWGROUP_ISP2\t8\n+#define TEGRA_SWGROUP_DC14\t9\t/* 0x490 *//* Exceptional non-linear */\n+#define TEGRA_SWGROUP_DC12\t10\t/* 0xa88 *//* Exceptional non-linear */\n+#define TEGRA_SWGROUP_MPE\t11\t/* 0x264 */\n+#define TEGRA_SWGROUP_MSENC\t11\n+#define TEGRA_SWGROUP_NV\t12\t/* 0x268 */\n+#define TEGRA_SWGROUP_NV2\t13\t/* 0x26c */\n+#define TEGRA_SWGROUP_PPCS\t14\t/* 0x270 */\n+#define TEGRA_SWGROUP_SATA2\t15\t/* 0x274 */\n+#define TEGRA_SWGROUP_SATA\t16\t/* 0x278 */\n+#define TEGRA_SWGROUP_VDE\t17\t/* 0x27c */\n+#define TEGRA_SWGROUP_VI\t18\t/* 0x280 */\n+#define TEGRA_SWGROUP_VIC\t19\t/* 0x284 */\n+#define TEGRA_SWGROUP_XUSB_HOST\t20\t/* 0x288 */\n+#define TEGRA_SWGROUP_XUSB_DEV\t21\t/* 0x28c */\n+#define TEGRA_SWGROUP_A9AVP\t22\t/* 0x290 */\n+#define TEGRA_SWGROUP_TSEC\t23\t/* 0x294 */\n+#define TEGRA_SWGROUP_PPCS1\t24\t/* 0x298 */\n+#define TEGRA_SWGROUP_SDMMC1A\t25\t/* 0xa94 *//* Linear shift again */\n+#define TEGRA_SWGROUP_SDMMC2A\t26\t/* 0xa98 */\n+#define TEGRA_SWGROUP_SDMMC3A\t27\t/* 0xa9c */\n+#define TEGRA_SWGROUP_SDMMC4A\t28\t/* 0xaa0 */\n+#define TEGRA_SWGROUP_ISP2B\t29\t/* 0xaa4 */\n+#define TEGRA_SWGROUP_GPU\t30\t/* 0xaa8 */\n+#define TEGRA_SWGROUP_GPUB\t31\t/* 0xaac */\n+#define TEGRA_SWGROUP_PPCS2\t32\t/* 0xab0 */\n+\n+#define TWO_U32_OF_U64(x)\t((x) & 0xffffffff) ((x) >> 32)\n+#define TEGRA_SWGROUP_BIT(x)\t(1ULL << TEGRA_SWGROUP_##x)\n+#define TEGRA_SWGROUP_CELLS(x)\tTWO_U32_OF_U64(TEGRA_SWGROUP_BIT(x))\n+\n+#define TEGRA_SWGROUP_MAX\t64\n+\n+#endif /* _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H */\n", "prefixes": [ "PATCHv8", "06/21" ] }