From patchwork Fri May 30 11:20:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 354078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 10B181400E2 for ; Fri, 30 May 2014 21:20:48 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752368AbaE3LUp (ORCPT ); Fri, 30 May 2014 07:20:45 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:3680 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752220AbaE3LUn (ORCPT ); Fri, 30 May 2014 07:20:43 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 30 May 2014 04:20:33 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 30 May 2014 04:13:30 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 30 May 2014 04:13:30 -0700 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 04:20:43 -0700 Received: from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com (10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 13:20:40 +0200 From: Hiroshi Doyu To: Subject: [PATCHv8 06/21] ARM: tegra: create a DT header defining SWGROUP ID Date: Fri, 30 May 2014 14:20:19 +0300 Message-ID: <1401448834-32659-7-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 2.0.0.rc1.15.g7e76a2f In-Reply-To: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> References: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. "swgroup" is a group of H/W clients which a Tegra SoC supports. This unique ID can be used to calculate MC_SMMU__ASID_0 register offset and MC__HOTRESET_*_0 register bit. This will allow the same header to be used by both device tree files, and drivers implementing this binding, which guarantees that the two stay in sync. This also makes device trees more readable by using names instead of magic numbers. For HOTRESET bit shifting we need another conversion table, which will come later. Signed-off-by: Hiroshi Doyu Cc: Mark Zhang --- include/dt-bindings/memory/tegra-swgroup.h | 50 ++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/dt-bindings/memory/tegra-swgroup.h diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h new file mode 100644 index 000000000000..32dd307e5f8e --- /dev/null +++ b/include/dt-bindings/memory/tegra-swgroup.h @@ -0,0 +1,50 @@ +/* + * This header provides constants for binding nvidia,swgroup ID + */ + +#ifndef _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H +#define _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H + +#define TEGRA_SWGROUP_AFI 0 /* 0x238 */ +#define TEGRA_SWGROUP_AVPC 1 /* 0x23c */ +#define TEGRA_SWGROUP_DC 2 /* 0x240 */ +#define TEGRA_SWGROUP_DCB 3 /* 0x244 */ +#define TEGRA_SWGROUP_EPP 4 /* 0x248 */ +#define TEGRA_SWGROUP_G2 5 /* 0x24c */ +#define TEGRA_SWGROUP_HC 6 /* 0x250 */ +#define TEGRA_SWGROUP_HDA 7 /* 0x254 */ +#define TEGRA_SWGROUP_ISP 8 /* 0x258 */ +#define TEGRA_SWGROUP_ISP2 8 +#define TEGRA_SWGROUP_DC14 9 /* 0x490 *//* Exceptional non-linear */ +#define TEGRA_SWGROUP_DC12 10 /* 0xa88 *//* Exceptional non-linear */ +#define TEGRA_SWGROUP_MPE 11 /* 0x264 */ +#define TEGRA_SWGROUP_MSENC 11 +#define TEGRA_SWGROUP_NV 12 /* 0x268 */ +#define TEGRA_SWGROUP_NV2 13 /* 0x26c */ +#define TEGRA_SWGROUP_PPCS 14 /* 0x270 */ +#define TEGRA_SWGROUP_SATA2 15 /* 0x274 */ +#define TEGRA_SWGROUP_SATA 16 /* 0x278 */ +#define TEGRA_SWGROUP_VDE 17 /* 0x27c */ +#define TEGRA_SWGROUP_VI 18 /* 0x280 */ +#define TEGRA_SWGROUP_VIC 19 /* 0x284 */ +#define TEGRA_SWGROUP_XUSB_HOST 20 /* 0x288 */ +#define TEGRA_SWGROUP_XUSB_DEV 21 /* 0x28c */ +#define TEGRA_SWGROUP_A9AVP 22 /* 0x290 */ +#define TEGRA_SWGROUP_TSEC 23 /* 0x294 */ +#define TEGRA_SWGROUP_PPCS1 24 /* 0x298 */ +#define TEGRA_SWGROUP_SDMMC1A 25 /* 0xa94 *//* Linear shift again */ +#define TEGRA_SWGROUP_SDMMC2A 26 /* 0xa98 */ +#define TEGRA_SWGROUP_SDMMC3A 27 /* 0xa9c */ +#define TEGRA_SWGROUP_SDMMC4A 28 /* 0xaa0 */ +#define TEGRA_SWGROUP_ISP2B 29 /* 0xaa4 */ +#define TEGRA_SWGROUP_GPU 30 /* 0xaa8 */ +#define TEGRA_SWGROUP_GPUB 31 /* 0xaac */ +#define TEGRA_SWGROUP_PPCS2 32 /* 0xab0 */ + +#define TWO_U32_OF_U64(x) ((x) & 0xffffffff) ((x) >> 32) +#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x) +#define TEGRA_SWGROUP_CELLS(x) TWO_U32_OF_U64(TEGRA_SWGROUP_BIT(x)) + +#define TEGRA_SWGROUP_MAX 64 + +#endif /* _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H */