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GET /api/patches/2232364/?format=api
{ "id": 2232364, "url": "http://patchwork.ozlabs.org/api/patches/2232364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-qom-tests-v2-42-ef7e3dc94f7a@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260504-qom-tests-v2-42-ef7e3dc94f7a@redhat.com>", "list_archive_url": null, "date": "2026-05-04T11:35:30", "name": "[v2,42/46] target/riscv: fix general_user_opts hash table leak", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f5612c2423e4d67ad6fd6c06b3eb05e7af3ac438", "submitter": { "id": 66774, "url": "http://patchwork.ozlabs.org/api/people/66774/?format=api", "name": "Marc-André Lureau", "email": "marcandre.lureau@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-qom-tests-v2-42-ef7e3dc94f7a@redhat.com/mbox/", "series": [ { "id": 502649, "url": "http://patchwork.ozlabs.org/api/series/502649/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502649", "date": "2026-05-04T11:34:48", "name": "Fix various QOM object life-cycle issues", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502649/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232364/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232364/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) 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"X-Scanned-By": "MIMEDefang 3.4.1 on 10.30.177.111", "Received-SPF": "pass client-ip=170.10.133.124;\n envelope-from=marcandre.lureau@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com", "X-Spam_score_int": "8", "X-Spam_score": "0.8", "X-Spam_bar": "/", "X-Spam_report": "(0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.444,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The global general_user_opts hash table is recreated on every\nriscv_cpu_init() call, leaking the previous one.\n\nFurthermore, the CPU settings should be associated with their instance\nand not global.\n\nAdd a finalize() to free associated instances.\n\nFixes: d167a2247ede (\"target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]\")\nSigned-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>\n---\n target/riscv/cpu.h | 3 ++-\n target/riscv/cpu.c | 51 +++++++++++++++++++++++++++-------------------\n target/riscv/kvm/kvm-cpu.c | 6 +++---\n 3 files changed, 35 insertions(+), 25 deletions(-)", "diff": "diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 81c41e34296..55a26aeb5be 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -546,6 +546,7 @@ struct ArchCPU {\n uint32_t pmu_avail_ctrs;\n /* Mapping of events to counters */\n GHashTable *pmu_event_ctr_map;\n+ GHashTable *user_options;\n const GPtrArray *decoders;\n };\n \n@@ -619,7 +620,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n bool probe, uintptr_t retaddr);\n char *riscv_isa_string(RISCVCPU *cpu);\n int riscv_cpu_max_xlen(RISCVCPUClass *mcc);\n-bool riscv_cpu_option_set(const char *optname);\n+bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname);\n \n #ifndef CONFIG_USER_ONLY\n void riscv_cpu_do_interrupt(CPUState *cpu);\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex ce15a17c37d..be9a3ac13e7 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -27,6 +27,7 @@\n #include \"qapi/error.h\"\n #include \"qapi/visitor.h\"\n #include \"qemu/error-report.h\"\n+#include \"qemu/timer.h\"\n #include \"hw/core/qdev-properties.h\"\n #include \"hw/core/qdev-prop-internal.h\"\n #include \"migration/vmstate.h\"\n@@ -59,18 +60,16 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu)\n return riscv_cpu_mxl(&cpu->env) == MXL_RV32;\n }\n \n-/* Hash that stores general user set numeric options */\n-static GHashTable *general_user_opts;\n-\n-static void cpu_option_add_user_setting(const char *optname, uint32_t value)\n+static void cpu_option_add_user_setting(RISCVCPU *cpu, const char *optname,\n+ uint32_t value)\n {\n- g_hash_table_insert(general_user_opts, (gpointer)optname,\n+ g_hash_table_insert(cpu->user_options, (gpointer)optname,\n GUINT_TO_POINTER(value));\n }\n \n-bool riscv_cpu_option_set(const char *optname)\n+bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname)\n {\n- return g_hash_table_contains(general_user_opts, optname);\n+ return g_hash_table_contains(cpu->user_options, optname);\n }\n \n #ifndef CONFIG_USER_ONLY\n@@ -1103,7 +1102,7 @@ static void riscv_cpu_init(Object *obj)\n \"riscv.cpu.rnmi\", RNMI_MAX);\n #endif /* CONFIG_USER_ONLY */\n \n- general_user_opts = g_hash_table_new(g_str_hash, g_str_equal);\n+ cpu->user_options = g_hash_table_new(g_str_hash, g_str_equal);\n \n /*\n * The timer and performance counters extensions were supported\n@@ -1453,7 +1452,7 @@ static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name,\n \n warn_report(\"\\\"pmu-num\\\" property is deprecated; use \\\"pmu-mask\\\"\");\n cpu->cfg.pmu_mask = pmu_mask;\n- cpu_option_add_user_setting(\"pmu-mask\", pmu_mask);\n+ cpu_option_add_user_setting(cpu, \"pmu-mask\", pmu_mask);\n }\n \n static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name,\n@@ -1495,7 +1494,7 @@ static void prop_pmu_mask_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.pmu_mask = value;\n }\n \n@@ -1527,7 +1526,7 @@ static void prop_mmu_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.mmu = value;\n }\n \n@@ -1559,7 +1558,7 @@ static void prop_pmp_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.pmp = value;\n }\n \n@@ -1599,7 +1598,7 @@ static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.pmp_regions = value;\n }\n \n@@ -1637,7 +1636,7 @@ static void prop_pmp_granularity_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.pmp_granularity = value;\n }\n \n@@ -1710,7 +1709,7 @@ static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, priv_version);\n+ cpu_option_add_user_setting(cpu, name, priv_version);\n cpu->env.priv_ver = priv_version;\n }\n \n@@ -1744,7 +1743,7 @@ static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, VEXT_VERSION_1_00_0);\n+ cpu_option_add_user_setting(cpu, name, VEXT_VERSION_1_00_0);\n cpu->env.vext_ver = VEXT_VERSION_1_00_0;\n }\n \n@@ -1787,7 +1786,7 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.vlenb = value >> 3;\n }\n \n@@ -1828,7 +1827,7 @@ static void prop_elen_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.elen = value;\n }\n \n@@ -1864,7 +1863,7 @@ static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.cbom_blocksize = value;\n }\n \n@@ -1900,7 +1899,7 @@ static void prop_cbop_blksize_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.cbop_blocksize = value;\n }\n \n@@ -1936,7 +1935,7 @@ static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n- cpu_option_add_user_setting(name, value);\n+ cpu_option_add_user_setting(cpu, name, value);\n cpu->cfg.cboz_blocksize = value;\n }\n \n@@ -2974,6 +2973,15 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)\n DEFINE_RISCV_CPU(type_name, parent_type_name, \\\n .profile = &(profile_))\n \n+static void riscv_cpu_instance_finalize(Object *obj)\n+{\n+ RISCVCPU *cpu = RISCV_CPU(obj);\n+\n+ g_clear_pointer(&cpu->pmu_timer, timer_free);\n+ g_clear_pointer(&cpu->pmu_event_ctr_map, g_hash_table_destroy);\n+ g_clear_pointer(&cpu->user_options, g_hash_table_destroy);\n+}\n+\n static const TypeInfo riscv_cpu_type_infos[] = {\n {\n .name = TYPE_RISCV_CPU,\n@@ -2981,6 +2989,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n .instance_size = sizeof(RISCVCPU),\n .instance_align = __alignof(RISCVCPU),\n .instance_init = riscv_cpu_init,\n+ .instance_finalize = riscv_cpu_instance_finalize,\n .abstract = true,\n .class_size = sizeof(RISCVCPUClass),\n .class_init = riscv_cpu_common_class_init,\ndiff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c\nindex b047ffa9c0c..e0241870ada 100644\n--- a/target/riscv/kvm/kvm-cpu.c\n+++ b/target/riscv/kvm/kvm-cpu.c\n@@ -2025,7 +2025,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n }\n \n if (cpu->cfg.ext_zicbom &&\n- riscv_cpu_option_set(kvm_cbom_blocksize.name)) {\n+ riscv_cpu_option_set(cpu, kvm_cbom_blocksize.name)) {\n \n reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,\n kvm_cbom_blocksize.kvm_reg_id);\n@@ -2044,7 +2044,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n }\n \n if (cpu->cfg.ext_zicboz &&\n- riscv_cpu_option_set(kvm_cboz_blocksize.name)) {\n+ riscv_cpu_option_set(cpu, kvm_cboz_blocksize.name)) {\n \n reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,\n kvm_cboz_blocksize.kvm_reg_id);\n@@ -2063,7 +2063,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n }\n \n /* Users are setting vlen, not vlenb */\n- if (riscv_has_ext(env, RVV) && riscv_cpu_option_set(\"vlen\")) {\n+ if (riscv_has_ext(env, RVV) && riscv_cpu_option_set(cpu, \"vlen\")) {\n if (!kvm_v_vlenb.supported) {\n error_setg(errp, \"Unable to set 'vlenb': register not supported\");\n return;\n", "prefixes": [ "v2", "42/46" ] }