[{"id":3685669,"web_url":"http://patchwork.ozlabs.org/comment/3685669/","msgid":"","list_archive_url":null,"date":"2026-05-04T11:53:43","subject":"Re: [PATCH v2 42/46] target/riscv: fix general_user_opts hash table\n leak","submitter":{"id":66774,"url":"http://patchwork.ozlabs.org/api/people/66774/","name":"Marc-André Lureau","email":"marcandre.lureau@redhat.com"},"content":"Hi\n\nOn Mon, May 4, 2026 at 3:39 PM Marc-André Lureau\n wrote:\n>\n> The global general_user_opts hash table is recreated on every\n> riscv_cpu_init() call, leaking the previous one.\n>\n> Furthermore, the CPU settings should be associated with their instance\n> and not global.\n>\n> Add a finalize() to free associated instances.\n>\n> Fixes: d167a2247ede (\"target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]\")\n> Signed-off-by: Marc-André Lureau \n> ---\n> target/riscv/cpu.h | 3 ++-\n> target/riscv/cpu.c | 51 +++++++++++++++++++++++++++-------------------\n> target/riscv/kvm/kvm-cpu.c | 6 +++---\n> 3 files changed, 35 insertions(+), 25 deletions(-)\n>\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 81c41e34296..55a26aeb5be 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -546,6 +546,7 @@ struct ArchCPU {\n> uint32_t pmu_avail_ctrs;\n> /* Mapping of events to counters */\n> GHashTable *pmu_event_ctr_map;\n> + GHashTable *user_options;\n> const GPtrArray *decoders;\n> };\n>\n> @@ -619,7 +620,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n> bool probe, uintptr_t retaddr);\n> char *riscv_isa_string(RISCVCPU *cpu);\n> int riscv_cpu_max_xlen(RISCVCPUClass *mcc);\n> -bool riscv_cpu_option_set(const char *optname);\n> +bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname);\n>\n> #ifndef CONFIG_USER_ONLY\n> void riscv_cpu_do_interrupt(CPUState *cpu);\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index ce15a17c37d..be9a3ac13e7 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -27,6 +27,7 @@\n> #include \"qapi/error.h\"\n> #include \"qapi/visitor.h\"\n> #include \"qemu/error-report.h\"\n> +#include \"qemu/timer.h\"\n> #include \"hw/core/qdev-properties.h\"\n> #include \"hw/core/qdev-prop-internal.h\"\n> #include \"migration/vmstate.h\"\n> @@ -59,18 +60,16 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu)\n> return riscv_cpu_mxl(&cpu->env) == MXL_RV32;\n> }\n>\n> -/* Hash that stores general user set numeric options */\n> -static GHashTable *general_user_opts;\n> -\n> -static void cpu_option_add_user_setting(const char *optname, uint32_t value)\n> +static void cpu_option_add_user_setting(RISCVCPU *cpu, const char *optname,\n> + uint32_t value)\n> {\n> - g_hash_table_insert(general_user_opts, (gpointer)optname,\n> + g_hash_table_insert(cpu->user_options, (gpointer)optname,\n> GUINT_TO_POINTER(value));\n> }\n>\n> -bool riscv_cpu_option_set(const char *optname)\n> +bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname)\n> {\n> - return g_hash_table_contains(general_user_opts, optname);\n> + return g_hash_table_contains(cpu->user_options, optname);\n> }\n>\n> #ifndef CONFIG_USER_ONLY\n> @@ -1103,7 +1102,7 @@ static void riscv_cpu_init(Object *obj)\n> \"riscv.cpu.rnmi\", RNMI_MAX);\n> #endif /* CONFIG_USER_ONLY */\n>\n> - general_user_opts = g_hash_table_new(g_str_hash, g_str_equal);\n> + cpu->user_options = g_hash_table_new(g_str_hash, g_str_equal);\n>\n> /*\n> * The timer and performance counters extensions were supported\n> @@ -1453,7 +1452,7 @@ static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name,\n>\n> warn_report(\"\\\"pmu-num\\\" property is deprecated; use \\\"pmu-mask\\\"\");\n> cpu->cfg.pmu_mask = pmu_mask;\n> - cpu_option_add_user_setting(\"pmu-mask\", pmu_mask);\n> + cpu_option_add_user_setting(cpu, \"pmu-mask\", pmu_mask);\n> }\n>\n> static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name,\n> @@ -1495,7 +1494,7 @@ static void prop_pmu_mask_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.pmu_mask = value;\n> }\n>\n> @@ -1527,7 +1526,7 @@ static void prop_mmu_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.mmu = value;\n> }\n>\n> @@ -1559,7 +1558,7 @@ static void prop_pmp_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.pmp = value;\n> }\n>\n> @@ -1599,7 +1598,7 @@ static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.pmp_regions = value;\n> }\n>\n> @@ -1637,7 +1636,7 @@ static void prop_pmp_granularity_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.pmp_granularity = value;\n> }\n>\n> @@ -1710,7 +1709,7 @@ static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, priv_version);\n> + cpu_option_add_user_setting(cpu, name, priv_version);\n> cpu->env.priv_ver = priv_version;\n> }\n>\n> @@ -1744,7 +1743,7 @@ static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, VEXT_VERSION_1_00_0);\n> + cpu_option_add_user_setting(cpu, name, VEXT_VERSION_1_00_0);\n> cpu->env.vext_ver = VEXT_VERSION_1_00_0;\n> }\n>\n> @@ -1787,7 +1786,7 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.vlenb = value >> 3;\n> }\n>\n> @@ -1828,7 +1827,7 @@ static void prop_elen_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.elen = value;\n> }\n>\n> @@ -1864,7 +1863,7 @@ static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.cbom_blocksize = value;\n> }\n>\n> @@ -1900,7 +1899,7 @@ static void prop_cbop_blksize_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.cbop_blocksize = value;\n> }\n>\n> @@ -1936,7 +1935,7 @@ static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *name,\n> return;\n> }\n>\n> - cpu_option_add_user_setting(name, value);\n> + cpu_option_add_user_setting(cpu, name, value);\n> cpu->cfg.cboz_blocksize = value;\n> }\n>\n> @@ -2974,6 +2973,15 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)\n> DEFINE_RISCV_CPU(type_name, parent_type_name, \\\n> .profile = &(profile_))\n>\n> +static void riscv_cpu_instance_finalize(Object *obj)\n> +{\n> + RISCVCPU *cpu = RISCV_CPU(obj);\n> +\n> + g_clear_pointer(&cpu->pmu_timer, timer_free);\n> + g_clear_pointer(&cpu->pmu_event_ctr_map, g_hash_table_destroy);\n\nThose 2 should be guarded with\n#ifndef CONFIG_USER_ONLY\n\nfixed\n\n> + g_clear_pointer(&cpu->user_options, g_hash_table_destroy);\n> +}\n> +\n> static const TypeInfo riscv_cpu_type_infos[] = {\n> {\n> .name = TYPE_RISCV_CPU,\n> @@ -2981,6 +2989,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n> .instance_size = sizeof(RISCVCPU),\n> .instance_align = __alignof(RISCVCPU),\n> .instance_init = riscv_cpu_init,\n> + .instance_finalize = riscv_cpu_instance_finalize,\n> .abstract = true,\n> .class_size = sizeof(RISCVCPUClass),\n> .class_init = riscv_cpu_common_class_init,\n> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c\n> index b047ffa9c0c..e0241870ada 100644\n> --- a/target/riscv/kvm/kvm-cpu.c\n> +++ b/target/riscv/kvm/kvm-cpu.c\n> @@ -2025,7 +2025,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> }\n>\n> if (cpu->cfg.ext_zicbom &&\n> - riscv_cpu_option_set(kvm_cbom_blocksize.name)) {\n> + riscv_cpu_option_set(cpu, kvm_cbom_blocksize.name)) {\n>\n> reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,\n> kvm_cbom_blocksize.kvm_reg_id);\n> @@ -2044,7 +2044,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> }\n>\n> if (cpu->cfg.ext_zicboz &&\n> - riscv_cpu_option_set(kvm_cboz_blocksize.name)) {\n> + riscv_cpu_option_set(cpu, kvm_cboz_blocksize.name)) {\n>\n> reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,\n> kvm_cboz_blocksize.kvm_reg_id);\n> @@ -2063,7 +2063,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n> }\n>\n> /* Users are setting vlen, not vlenb */\n> - if (riscv_has_ext(env, RVV) && riscv_cpu_option_set(\"vlen\")) {\n> + if (riscv_has_ext(env, RVV) && riscv_cpu_option_set(cpu, \"vlen\")) {\n> if (!kvm_v_vlenb.supported) {\n> error_setg(errp, \"Unable to set 'vlenb': register not supported\");\n> return;\n>\n> --\n> 2.54.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=QRZ526D4;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=google header.b=ZdSK0PxA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n 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