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GET /api/patches/2230880/?format=api
{ "id": 2230880, "url": "http://patchwork.ozlabs.org/api/patches/2230880/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-4-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260430071315.354333-4-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-04-30T07:12:59", "name": "[v4,03/15] vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d6dcbea5f200ee2577677ed1f4bdcfb036109f8", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-4-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 502222, "url": "http://patchwork.ozlabs.org/api/series/502222/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502222", "date": "2026-04-30T07:12:57", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502222/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230880/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=BGT14pJb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5lpJ3kN5z1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 17:16:24 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wILbQ-0005OO-6N; Thu, 30 Apr 2026 03:14:28 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1wILam-00058N-1y\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 03:13:51 -0400", "from mgamail.intel.com ([192.198.163.13])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1wILaj-0008IJ-7M\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 03:13:47 -0400", "from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:13:43 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:13:40 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777533225; x=1809069225;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=WFgpWH3Lzh77PiPSeGLuAnB2U0goGkEoiXkGm0T8WVA=;\n b=BGT14pJbO64VMWBVmjTgYCn1iRdk4QqqwGQ4ZG1SppS7gSw1PuF070mN\n lpZv9KtVFIY3NaUhr6AP6u1qc/MUMoNK7Muu23tx+kYhRJg+CS5pNKkqE\n H6kCnfQ6KOxh2ADXzZcwgjw/+xQVE/Btl4aV6ISzLMVaF7/RskwOBjaWf\n bahZMchwWPf7xEgfgNkt71VZS6EOji4JGAWcTXiXApN0Xp6aF11uqZXqf\n tQ++vDRugL64jJy7f8pRrkdkWd2BvtP+OmI9d9lAHMXj2jO68fcUdNud1\n LIMpKeU9p1LlCOHmaAE3oA4/4vqLhbD3jmiBcXo5aZbkFEcoX3InrWRo0 A==;", "X-CSE-ConnectionGUID": [ "kkOlo/ENSmSD8GpoNT9nuA==", "24iJRBIeSrmod/zhjjX2Gw==" ], "X-CSE-MsgGUID": [ "E90wHr1BQM+4ymKG0dk8ZA==", "eAyCTGDJQy+h5OZ3Sb+jMA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11771\"; a=\"81051585\"", "E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"81051585\"", "E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"234771472\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v4 03/15] vfio/iommufd: Create nesting parent hwpt with\n IOMMU_HWPT_ALLOC_PASID flag", "Date": "Thu, 30 Apr 2026 03:12:59 -0400", "Message-ID": "<20260430071315.354333-4-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260430071315.354333-1-zhenzhong.duan@intel.com>", "References": "<20260430071315.354333-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.13;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When both device and vIOMMU have PASID enabled, then guest may setup\npasid attached translation.\n\nVFIO needs to be aware of potential pasid usage and should attach the\nnon-pasid part of pasid-capable device to hwpt flagged with\nIOMMU_HWPT_ALLOC_PASID.\n\nARM SMMU doesn't support IOMMU_HWPT_ALLOC_PASID, only VTD need it. So\nwe can't check the existing vIOMMU flag VIOMMU_FLAG_PASID_SUPPORTED to\ndetermine if set flag IOMMU_HWPT_ALLOC_PASID. Instead, introduce a new\nflag VIOMMU_FLAG_WANT_PASID_ATTACH which will only be exposed by VTD.\n\nOpportunistically add documentation for VIOMMU_FLAG_PASID_SUPPORTED\nand explain the difference with VIOMMU_FLAG_WANT_PASID_ATTACH.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Yi Liu <yi.l.liu@intel.com>\nTested-by: Xudong Hao <xudong.hao@intel.com>\n---\n include/hw/core/iommu.h | 11 +++++++++++\n include/hw/vfio/vfio-device.h | 1 +\n hw/vfio/device.c | 11 +++++++++++\n hw/vfio/iommufd.c | 8 +++++++-\n 4 files changed, 30 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/core/iommu.h b/include/hw/core/iommu.h\nindex 77739d4214..20d6d79062 100644\n--- a/include/hw/core/iommu.h\n+++ b/include/hw/core/iommu.h\n@@ -20,9 +20,20 @@\n enum viommu_flags {\n /* vIOMMU needs nesting parent HWPT to create nested HWPT */\n VIOMMU_FLAG_WANT_NESTING_PARENT = BIT_ULL(0),\n+ /*\n+ * vIOMMU supports PASID capability, VFIO checks this flag and synthesize\n+ * a PASID capability.\n+ */\n VIOMMU_FLAG_PASID_SUPPORTED = BIT_ULL(1),\n /* vIOMMU needs dirty tracking on the nesting parent HWPT for nested use */\n VIOMMU_FLAG_WANT_NESTING_DIRTY_TRACKING = BIT_ULL(2),\n+ /*\n+ * vIOMMU requests other sub-system like VFIO to create a HWPT that can be\n+ * used with PASID attachment. VIOMMU_FLAG_PASID_SUPPORTED can't be used\n+ * for this purpose as PASID attachment is needed by VTD IOMMU but not ARM\n+ * SMMU.\n+ */\n+ VIOMMU_FLAG_WANT_PASID_ATTACH = BIT_ULL(3),\n };\n \n /* Host IOMMU quirks. Extracted from host IOMMU capabilities */\ndiff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h\nindex 380a55d6e5..8472420d3f 100644\n--- a/include/hw/vfio/vfio-device.h\n+++ b/include/hw/vfio/vfio-device.h\n@@ -282,6 +282,7 @@ void vfio_device_unprepare(VFIODevice *vbasedev);\n \n bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev);\n bool vfio_device_get_viommu_flags_want_nesting_dirty(VFIODevice *vbasedev);\n+bool vfio_device_get_viommu_flags_want_pasid_attach(VFIODevice *vbasedev);\n bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev,\n uint32_t type, void *caps,\n uint32_t size);\ndiff --git a/hw/vfio/device.c b/hw/vfio/device.c\nindex 3ffd69a579..b954b44d31 100644\n--- a/hw/vfio/device.c\n+++ b/hw/vfio/device.c\n@@ -544,6 +544,17 @@ bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev)\n return false;\n }\n \n+bool vfio_device_get_viommu_flags_want_pasid_attach(VFIODevice *vbasedev)\n+{\n+ VFIOPCIDevice *vdev = vfio_pci_from_vfio_device(vbasedev);\n+\n+ if (vdev) {\n+ return !!(pci_device_get_viommu_flags(PCI_DEVICE(vdev)) &\n+ VIOMMU_FLAG_WANT_PASID_ATTACH);\n+ }\n+ return false;\n+}\n+\n bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev,\n uint32_t type, void *caps,\n uint32_t size)\ndiff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c\nindex 78e7b6a045..0718f029ca 100644\n--- a/hw/vfio/iommufd.c\n+++ b/hw/vfio/iommufd.c\n@@ -364,6 +364,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,\n VendorCaps caps;\n VFIOIOASHwpt *hwpt;\n uint32_t hwpt_id;\n+ uint8_t max_pasid_log2 = 0;\n int ret;\n \n /* Try to find a domain */\n@@ -409,7 +410,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,\n */\n if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devid,\n &type, &caps, sizeof(caps), &hw_caps,\n- NULL, errp)) {\n+ &max_pasid_log2, errp)) {\n return false;\n }\n \n@@ -437,6 +438,11 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,\n }\n }\n \n+ if (max_pasid_log2 &&\n+ vfio_device_get_viommu_flags_want_pasid_attach(vbasedev)) {\n+ flags |= IOMMU_HWPT_ALLOC_PASID;\n+ }\n+\n if (cpr_is_incoming()) {\n hwpt_id = vbasedev->cpr.hwpt_id;\n goto skip_alloc;\n", "prefixes": [ "v4", "03/15" ] }