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GET /api/patches/2230589/?format=api
{ "id": 2230589, "url": "http://patchwork.ozlabs.org/api/patches/2230589/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260429215614.1793131-1-bwicaksono@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260429215614.1793131-1-bwicaksono@nvidia.com>", "list_archive_url": null, "date": "2026-04-29T21:56:14", "name": "[v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40c466372b3182838dad58099f754b7078486f40", "submitter": { "id": 83903, "url": "http://patchwork.ozlabs.org/api/people/83903/?format=api", "name": "Besar Wicaksono", "email": "bwicaksono@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260429215614.1793131-1-bwicaksono@nvidia.com/mbox/", "series": [ { "id": 502158, "url": "http://patchwork.ozlabs.org/api/series/502158/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502158", "date": "2026-04-29T21:56:14", "name": "[v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502158/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230589/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230589/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-14064-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=DMYNw2S7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Besar Wicaksono <bwicaksono@nvidia.com>", "To": "<will@kernel.org>, <mark.rutland@arm.com>, <james.clark@linaro.org>,\n\t<yangyccccc@gmail.com>", "CC": "<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <treding@nvidia.com>, <jonathanh@nvidia.com>,\n\t<vsethi@nvidia.com>, <rwiley@nvidia.com>, <sdonthineni@nvidia.com>,\n\t<mochs@nvidia.com>, <nirmoyd@nvidia.com>, <skelley@nvidia.com>, \"Besar\n Wicaksono\" <bwicaksono@nvidia.com>", "Subject": "[PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "Date": "Wed, 29 Apr 2026 21:56:14 +0000", "Message-ID": "<20260429215614.1793131-1-bwicaksono@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN3PEPF0000B06B:EE_|SN7PR12MB8002:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d02e2cdc-e4ff-43cd-cb45-08dea63a32f3", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|18002099003|56012099003|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n\tFC+/3YeyV4eNhEjsuqBAugq0tYtfTzb5whoBYSyeBXlq9Bp8Mp5pgzLR5RR4nWS3ImKPD5kVmgP3CDoFC9ktB8rt+eGv7vPUNvHE0JvFNJJmnDCqvaEnS17loa5oIkyfQCQyL0r74PWy2BgnIhGGEWZXDswiHrL+Jr0Tj/1K3InBfNJ7QzZUF/sTSVndnATIqNjrf4TGtak7NTai49a4ugzJ5ICvgBe/g11kvFgLVWBHdiJ10hK7ZZBKVlcsDCbnpYsUmLId5ryfZCJEGDZu0+AhxQGxS67fMCG1IBg9qFfC1tc5DdctxSN6ckFCu/VbmYwieh0iATEPd6ScehX6MKm0/4upgfr0uSGkF/PwTk7JLgM0icladqBn12OrCWoD14mGA8aioaRJSt6UmA+EoIbaFENZGF5CzQon9DfRenVj2Wzvl+PztWF2qOWi8x81n1LotPSVUygp9x2E+A9OcoJRzEt0kaKpBciojRpWO2feLbqOQo4uD5xMD1l5dBHOWoPfz+N9wq1AljJJjXvWo8vpSyHXjUHpoJTsku5QMZwfHdAKNRZcW9/ropPg6lAzjjTasRd10cfuxiGG7qNGRgOnN9EE7o5qUgpTySrjz+dE4+zHQLJrrLeADWElUYqdVF4bKR40Fqhic5LNQtX8L2TgBwmIkwkNSGktgLfdtb3CKkhqoBi0JrNhz8NT3zZmnHbtRo/Bd2FhxxBhM3T1LgmxNo/du4FSrvjFrrm5aOk+4rxRCJPaOBhXrRZTu6xK", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(18002099003)(56012099003)(13003099007);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tyPTSiPLt7bnmxP5CiZORK1J0eDZi8z0PavULK+MelmZ5hs0fmI0IA95q86nH6ADb5/tlbZnLxIugTxr2hN5rYmaCCutw24eUiQCoHBFFMqiZ1w0gC/RBxid62dBcdyF3nRRZpEfduYnc9GM1kVgsuIiqD9HwPEzHciKaUYOHMAT0z8F+Fph3UIM9Mpe+AohxjI0PMj1+BvLLSBeLVPjtypXvhuH21nYFkGX8V7QBP4MY6NTM9N2EOuOYjUJQ9291+4FqbTREWt8bC3bXWQhhcGmutCtsb4a/MAqztBdDuJlBXdBz1iq286xhYQeDzBN7m2GqvVXPQcMDzN2ymgNubCz9Skz2sliuwVDKUmnHKWtncuMd7+K0SBB+OKLrv0PvqAE7bq/l4v3VMyMvLNqTmKrbpfMVpde8dh0zMYfCAwRarBt9u3XqP1Occ2Oc7y7/", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Apr 2026 21:56:42.4554\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d02e2cdc-e4ff-43cd-cb45-08dea63a32f3", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN3PEPF0000B06B.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB8002" }, "content": "PMCCNTR_EL0 may continue to increment on NVIDIA Olympus CPUs while the\nPE is in WFI/WFE. That does not necessarily match the CPU_CYCLES event\ncounted by a programmable counter, so using PMCCNTR_EL0 for cycles can\ngive results that differ from the programmable counter path.\n\nExtend the existing PMCCNTR avoidance decision from the SMT case to\nalso cover Olympus. Store the result in the common arm_pmu state at\nregistration time, so arm_pmuv3 can keep using a single flag when\ndeciding whether CPU_CYCLES may use PMCCNTR_EL0.\n\nUse the cached MIDR from cpu_data to identify Olympus parts and avoid\nreading MIDR_EL1 in the event path.\n\nSigned-off-by: Besar Wicaksono <bwicaksono@nvidia.com>\n---\n\nChanges from v1:\n * add CONFIG_ARM64 check to fix build error found by kernel test robot\n * add explicit include of <asm/cputype.h>\nv1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-bwicaksono@nvidia.com/\n\nChanges from v2:\n * Move the Olympus PMCCNTR avoidance check from arm_pmuv3.c to the\n common arm_pmu registration path.\n * Replace the PMUv3-only has_smt flag with avoid_pmccntr, covering both\n the existing SMT restriction and the Olympus MIDR restriction.\n * Use the cached per-CPU MIDR from cpu_data instead of calling\n is_midr_in_range_list() from armv8pmu_can_use_pmccntr().\n * Add the required asm/cpu.h include for cpu_data.\n * Drop the use_pmccntr override patch from this revision.\nv2: https://lore.kernel.org/linux-arm-kernel/20260421203856.3539186-1-bwicaksono@nvidia.com/#t\n\n---\n drivers/perf/arm_pmu.c | 78 +++++++++++++++++++++++++++++++++---\n drivers/perf/arm_pmuv3.c | 8 +---\n include/linux/perf/arm_pmu.h | 2 +-\n 3 files changed, 75 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c\nindex 939bcbd433aa..7df185ee7b74 100644\n--- a/drivers/perf/arm_pmu.c\n+++ b/drivers/perf/arm_pmu.c\n@@ -24,6 +24,8 @@\n #include <linux/irq.h>\n #include <linux/irqdesc.h>\n \n+#include <asm/cpu.h>\n+#include <asm/cputype.h>\n #include <asm/irq_regs.h>\n \n static int armpmu_count_irq_users(const struct cpumask *affinity,\n@@ -920,6 +922,76 @@ void armpmu_free(struct arm_pmu *pmu)\n \tkfree(pmu);\n }\n \n+#ifdef CONFIG_ARM64\n+/*\n+ * List of CPUs that should avoid using PMCCNTR_EL0.\n+ */\n+static struct midr_range armpmu_avoid_pmccntr_cpus[] = {\n+\t/*\n+\t * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state.\n+\t * This is an implementation specific behavior and not an erratum.\n+\t *\n+\t * From ARM DDI0487 D14.4:\n+\t * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count\n+\t * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n+\t *\n+\t * From ARM DDI0487 D24.5.2:\n+\t * All counters are subject to any changes in clock frequency, including\n+\t * clock stopping caused by the WFI and WFE instructions.\n+\t * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n+\t * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and\n+\t * WFE instructions.\n+\t */\n+\tMIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n+\t{}\n+};\n+\n+static bool armpmu_is_in_avoid_pmccntr_cpus(int cpu)\n+{\n+\tstruct midr_range const *r = armpmu_avoid_pmccntr_cpus;\n+\tu32 midr = (u32)per_cpu(cpu_data, cpu).reg_midr;\n+\n+\twhile (r->model) {\n+\t\tif (midr_is_cpu_model_range(midr, r->model, r->rv_min, r->rv_max))\n+\t\t\treturn true;\n+\t\tr++;\n+\t}\n+\n+\treturn false;\n+}\n+#else\n+static bool armpmu_is_in_avoid_pmccntr_cpus(int cpu)\n+{\n+\treturn false;\n+}\n+#endif\n+\n+static bool armpmu_avoid_pmccntr(struct arm_pmu *pmu)\n+{\n+\tint cpu = cpumask_first(&pmu->supported_cpus);\n+\n+\t/*\n+\t * By this stage we know our supported CPUs on either DT/ACPI platforms,\n+\t * detect the SMT implementation.\n+\t * On SMT CPUs, the PMCCNTR_EL0 increments from the processor clock rather\n+\t * than the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue\n+\t * counting on a WFI PE if one of its SMT sibling is not idle on a\n+\t * multi-threaded implementation. So don't use it on SMT cores.\n+\t */\n+\tif (topology_core_has_smt(cpu))\n+\t\treturn true;\n+\n+\t/*\n+\t * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES\n+\t * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to\n+\t * prevent inconsistency in the results.\n+\t */\n+\tif (armpmu_is_in_avoid_pmccntr_cpus(cpu))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n int armpmu_register(struct arm_pmu *pmu)\n {\n \tint ret;\n@@ -928,11 +1000,7 @@ int armpmu_register(struct arm_pmu *pmu)\n \tif (ret)\n \t\treturn ret;\n \n-\t/*\n-\t * By this stage we know our supported CPUs on either DT/ACPI platforms,\n-\t * detect the SMT implementation.\n-\t */\n-\tpmu->has_smt = topology_core_has_smt(cpumask_first(&pmu->supported_cpus));\n+\tpmu->avoid_pmccntr = armpmu_avoid_pmccntr(pmu);\n \n \tif (!pmu->set_event_filter)\n \t\tpmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;\ndiff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\nindex 8014ff766cff..60f159a51992 100644\n--- a/drivers/perf/arm_pmuv3.c\n+++ b/drivers/perf/arm_pmuv3.c\n@@ -1002,13 +1002,7 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n \tif (has_branch_stack(event))\n \t\treturn false;\n \n-\t/*\n-\t * The PMCCNTR_EL0 increments from the processor clock rather than\n-\t * the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue\n-\t * counting on a WFI PE if one of its SMT sibling is not idle on a\n-\t * multi-threaded implementation. So don't use it on SMT cores.\n-\t */\n-\tif (cpu_pmu->has_smt)\n+\tif (cpu_pmu->avoid_pmccntr)\n \t\treturn false;\n \n \treturn true;\ndiff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h\nindex 52b37f7bdbf9..02d2c7f45b52 100644\n--- a/include/linux/perf/arm_pmu.h\n+++ b/include/linux/perf/arm_pmu.h\n@@ -119,7 +119,7 @@ struct arm_pmu {\n \n \t/* PMUv3 only */\n \tint\t\tpmuver;\n-\tbool\t\thas_smt;\n+\tbool\t\tavoid_pmccntr;\n \tu64\t\treg_pmmir;\n \tu64\t\treg_brbidr;\n #define ARMV8_PMUV3_MAX_COMMON_EVENTS\t\t0x40\n", "prefixes": [ "v3" ] }