[{"id":3684992,"web_url":"http://patchwork.ozlabs.org/comment/3684992/","msgid":"<4BC7B5BD-9160-4A6A-B18F-E788CF340E8A@nvidia.com>","list_archive_url":null,"date":"2026-05-01T00:27:18","subject":"Re: [PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":88564,"url":"http://patchwork.ozlabs.org/api/people/88564/","name":"Matt Ochs","email":"mochs@nvidia.com"},"content":"> On Apr 29, 2026, at 16:56, Besar Wicaksono wrote:\n> \n> PMCCNTR_EL0 may continue to increment on NVIDIA Olympus CPUs while the\n> PE is in WFI/WFE. That does not necessarily match the CPU_CYCLES event\n> counted by a programmable counter, so using PMCCNTR_EL0 for cycles can\n> give results that differ from the programmable counter path.\n> \n> Extend the existing PMCCNTR avoidance decision from the SMT case to\n> also cover Olympus. Store the result in the common arm_pmu state at\n> registration time, so arm_pmuv3 can keep using a single flag when\n> deciding whether CPU_CYCLES may use PMCCNTR_EL0.\n> \n> Use the cached MIDR from cpu_data to identify Olympus parts and avoid\n> reading MIDR_EL1 in the event path.\n> \n> Signed-off-by: Besar Wicaksono \n\nVerified on NVIDIA Vera (Olympus CPUs) with UEFI SMT disabled. Confirmed\nthat grouped cpu_cycles events show ~1x ratio (both on programmable\ncounters) with the patch vs ~15x inflation without it.\n\nTested-by: Matthew R. Ochs ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=e2zCkzJ1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14125-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"e2zCkzJ1\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.201.17","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6Bh03GWjz1y1d\n\tfor ; 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smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=e2zCkzJ1; arc=fail smtp.client-ip=40.107.201.17","i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=VmoGKkI7NuJwulbhvTqV0QTHX+4aatQIeLcAJQ/xayA=;\n b=e2zCkzJ1h4e2sZNiigbtO7FJldd9OUZmziplNY0amdHBUa79kZ1O1WOMsgWmuPHB9dme+CcyByFymKcr9CoRinvCFqYVkQQF1FRL6eh6LP5y8KDuHLdT6HIXi5UWtwMjNQVL+qilp3W/cJK3+LJIIPfpaGrPeOEYfP0BMqAj8gOSBcTOod+3JOCKN2GTZhi/rimbzbiasB8FYDeYqv4/IrxyvpA/GIB/Dxk6v/nsOow2q1qYy1ydN554dN24vfZCGOooLpPMb9Vraaf1o4oLAQuXUDksyjBP2lrumKLuRude0RHqkFPRe0G0TpQHcnLEkM3lPxzdE+aLpkNhZ0WAOg==","From":"Matt Ochs ","To":"Besar Wicaksono ","CC":"\"will@kernel.org\" , \"mark.rutland@arm.com\"\n\t, \"james.clark@linaro.org\" ,\n\t\"yangyccccc@gmail.com\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \"linux-kernel@vger.kernel.org\"\n\t, \"linux-tegra@vger.kernel.org\"\n\t, Thierry Reding , Jon\n Hunter , Vikram Sethi , Rich Wiley\n\t, Shanker Donthineni , Nirmoy Das\n\t, Sean Kelley ","Subject":"Re: [PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","Thread-Topic":"[PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","Thread-Index":"AQHc2CMVnUUPaHwN1E6xtk7y25sENLX4UjWA","Date":"Fri, 1 May 2026 00:27:18 +0000","Message-ID":"<4BC7B5BD-9160-4A6A-B18F-E788CF340E8A@nvidia.com>","References":"<20260429215614.1793131-1-bwicaksono@nvidia.com>","In-Reply-To":"<20260429215614.1793131-1-bwicaksono@nvidia.com>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=e2zCkzJ1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"us-ascii\"","Content-ID":"<5C3220BB1279BE4EA63CEBA5172FFCD5@namprd12.prod.outlook.com>","Content-Transfer-Encoding":"quoted-printable","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"DS0PR12MB8442.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n e632dc8b-7cbd-4f51-3956-08dea7186704","X-MS-Exchange-CrossTenant-originalarrivaltime":"01 May 2026 00:27:18.2270\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n M3SGhK6FDB1HseCQeKlHjgDsm/2L/JjqMDGNW3AbVzUpXLjV6U7uF+ZqBAGDAoxDQEak/43eAHmFy+5CUzikjw==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV8PR12MB9449"}},{"id":3685135,"web_url":"http://patchwork.ozlabs.org/comment/3685135/","msgid":"<0fc8ae87-a941-4dfe-9c14-c851c6a29514@linaro.org>","list_archive_url":null,"date":"2026-05-01T14:01:42","subject":"Re: [PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":88902,"url":"http://patchwork.ozlabs.org/api/people/88902/","name":"James Clark","email":"james.clark@linaro.org"},"content":"On 29/04/2026 10:56 pm, Besar Wicaksono wrote:\n> PMCCNTR_EL0 may continue to increment on NVIDIA Olympus CPUs while the\n> PE is in WFI/WFE. That does not necessarily match the CPU_CYCLES event\n> counted by a programmable counter, so using PMCCNTR_EL0 for cycles can\n> give results that differ from the programmable counter path.\n> \n> Extend the existing PMCCNTR avoidance decision from the SMT case to\n> also cover Olympus. Store the result in the common arm_pmu state at\n> registration time, so arm_pmuv3 can keep using a single flag when\n> deciding whether CPU_CYCLES may use PMCCNTR_EL0.\n> \n> Use the cached MIDR from cpu_data to identify Olympus parts and avoid\n> reading MIDR_EL1 in the event path.\n> \n> Signed-off-by: Besar Wicaksono \n> ---\n> \n> Changes from v1:\n> * add CONFIG_ARM64 check to fix build error found by kernel test robot\n> * add explicit include of \n> v1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-bwicaksono@nvidia.com/\n> \n> Changes from v2:\n> * Move the Olympus PMCCNTR avoidance check from arm_pmuv3.c to the\n> common arm_pmu registration path.\n> * Replace the PMUv3-only has_smt flag with avoid_pmccntr, covering both\n> the existing SMT restriction and the Olympus MIDR restriction.\n> * Use the cached per-CPU MIDR from cpu_data instead of calling\n> is_midr_in_range_list() from armv8pmu_can_use_pmccntr().\n> * Add the required asm/cpu.h include for cpu_data.\n> * Drop the use_pmccntr override patch from this revision.\n> v2: https://lore.kernel.org/linux-arm-kernel/20260421203856.3539186-1-bwicaksono@nvidia.com/#t\n> \n> ---\n> drivers/perf/arm_pmu.c | 78 +++++++++++++++++++++++++++++++++---\n> drivers/perf/arm_pmuv3.c | 8 +---\n> include/linux/perf/arm_pmu.h | 2 +-\n> 3 files changed, 75 insertions(+), 13 deletions(-)\n> \n> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c\n> index 939bcbd433aa..7df185ee7b74 100644\n> --- a/drivers/perf/arm_pmu.c\n> +++ b/drivers/perf/arm_pmu.c\n> @@ -24,6 +24,8 @@\n> #include \n> #include \n> \n> +#include \n> +#include \n> #include \n> \n> static int armpmu_count_irq_users(const struct cpumask *affinity,\n> @@ -920,6 +922,76 @@ void armpmu_free(struct arm_pmu *pmu)\n> \tkfree(pmu);\n> }\n> \n> +#ifdef CONFIG_ARM64\n> +/*\n> + * List of CPUs that should avoid using PMCCNTR_EL0.\n> + */\n> +static struct midr_range armpmu_avoid_pmccntr_cpus[] = {\n> +\t/*\n> +\t * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state.\n> +\t * This is an implementation specific behavior and not an erratum.\n> +\t *\n> +\t * From ARM DDI0487 D14.4:\n> +\t * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count\n> +\t * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n> +\t *\n> +\t * From ARM DDI0487 D24.5.2:\n> +\t * All counters are subject to any changes in clock frequency, including\n> +\t * clock stopping caused by the WFI and WFE instructions.\n> +\t * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n> +\t * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and\n> +\t * WFE instructions.\n> +\t */\n> +\tMIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n> +\t{}\n> +};\n> +\n> +static bool armpmu_is_in_avoid_pmccntr_cpus(int cpu)\n> +{\n> +\tstruct midr_range const *r = armpmu_avoid_pmccntr_cpus;\n> +\tu32 midr = (u32)per_cpu(cpu_data, cpu).reg_midr;\n\nHi Besar,\n\nThis is still fragile to the thing I mentioned on V2 about some of the \nCPUs not being online, then cpu_data isn't initialized for those CPUs.\n\nSashiko suggests to use cpumask_any_and(&pmu->supported_cpus, \ncpu_online_mask), and currently the Arm PMUs do require at least one CPU \nonline so it's probably fine. Although it could be fragile if we added \ndeferred probing in the future.\n\nThe other alternative is to put this in __armv8pmu_probe_pmu(), although \nthen you end up with both arm_pmuv3 and arm_pmu initializing \ncpu_pmu->has_smt, but I'm sure there is a way to make it fit somehow.\n\nJames\n\n> +\n> +\twhile (r->model) {\n> +\t\tif (midr_is_cpu_model_range(midr, r->model, r->rv_min, r->rv_max))\n> +\t\t\treturn true;\n> +\t\tr++;\n> +\t}\n> +\n> +\treturn false;\n> +}\n> +#else\n> +static bool armpmu_is_in_avoid_pmccntr_cpus(int cpu)\n> +{\n> +\treturn false;\n> +}\n> +#endif\n> +\n> +static bool armpmu_avoid_pmccntr(struct arm_pmu *pmu)\n> +{\n> +\tint cpu = cpumask_first(&pmu->supported_cpus);\n> +\n> +\t/*\n> +\t * By this stage we know our supported CPUs on either DT/ACPI platforms,\n> +\t * detect the SMT implementation.\n> +\t * On SMT CPUs, the PMCCNTR_EL0 increments from the processor clock rather\n> +\t * than the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue\n> +\t * counting on a WFI PE if one of its SMT sibling is not idle on a\n> +\t * multi-threaded implementation. So don't use it on SMT cores.\n> +\t */\n> +\tif (topology_core_has_smt(cpu))\n> +\t\treturn true;\n> +\n> +\t/*\n> +\t * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES\n> +\t * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to\n> +\t * prevent inconsistency in the results.\n> +\t */\n> +\tif (armpmu_is_in_avoid_pmccntr_cpus(cpu))\n> +\t\treturn true;\n> +\n> +\treturn false;\n> +}\n> +\n> int armpmu_register(struct arm_pmu *pmu)\n> {\n> \tint ret;\n> @@ -928,11 +1000,7 @@ int armpmu_register(struct arm_pmu *pmu)\n> \tif (ret)\n> \t\treturn ret;\n> \n> -\t/*\n> -\t * By this stage we know our supported CPUs on either DT/ACPI platforms,\n> -\t * detect the SMT implementation.\n> -\t */\n> -\tpmu->has_smt = topology_core_has_smt(cpumask_first(&pmu->supported_cpus));\n> +\tpmu->avoid_pmccntr = armpmu_avoid_pmccntr(pmu);\n> \n> \tif (!pmu->set_event_filter)\n> \t\tpmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;\n> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\n> index 8014ff766cff..60f159a51992 100644\n> --- a/drivers/perf/arm_pmuv3.c\n> +++ b/drivers/perf/arm_pmuv3.c\n> @@ -1002,13 +1002,7 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n> \tif (has_branch_stack(event))\n> \t\treturn false;\n> \n> -\t/*\n> -\t * The PMCCNTR_EL0 increments from the processor clock rather than\n> -\t * the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue\n> -\t * counting on a WFI PE if one of its SMT sibling is not idle on a\n> -\t * multi-threaded implementation. So don't use it on SMT cores.\n> -\t */\n> -\tif (cpu_pmu->has_smt)\n> +\tif (cpu_pmu->avoid_pmccntr)\n> \t\treturn false;\n> \n> \treturn true;\n> diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h\n> index 52b37f7bdbf9..02d2c7f45b52 100644\n> --- a/include/linux/perf/arm_pmu.h\n> +++ b/include/linux/perf/arm_pmu.h\n> @@ -119,7 +119,7 @@ struct arm_pmu {\n> \n> \t/* PMUv3 only */\n> \tint\t\tpmuver;\n> -\tbool\t\thas_smt;\n> +\tbool\t\tavoid_pmccntr;\n> \tu64\t\treg_pmmir;\n> \tu64\t\treg_brbidr;\n> #define ARMV8_PMUV3_MAX_COMMON_EVENTS\t\t0x40","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=kHvDN6LE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":3685229,"web_url":"http://patchwork.ozlabs.org/comment/3685229/","msgid":"","list_archive_url":null,"date":"2026-05-01T21:25:30","subject":"RE: [PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":83903,"url":"http://patchwork.ozlabs.org/api/people/83903/","name":"Besar Wicaksono","email":"bwicaksono@nvidia.com"},"content":"> -----Original Message-----\n> From: James Clark \n> Sent: Friday, May 1, 2026 9:02 AM\n> To: Besar Wicaksono \n> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-\n> tegra@vger.kernel.org; Thierry Reding ; Jon Hunter\n> ; Vikram Sethi ; Rich Wiley\n> ; Shanker Donthineni ; Matt\n> Ochs ; Nirmoy Das ; Sean Kelley\n> ; will@kernel.org; mark.rutland@arm.com;\n> yangyccccc@gmail.com\n> Subject: Re: [PATCH v3] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA\n> Olympus\n> \n> External email: Use caution opening links or attachments\n> \n> \n> On 29/04/2026 10:56 pm, Besar Wicaksono wrote:\n> > PMCCNTR_EL0 may continue to increment on NVIDIA Olympus CPUs while\n> the\n> > PE is in WFI/WFE. That does not necessarily match the CPU_CYCLES event\n> > counted by a programmable counter, so using PMCCNTR_EL0 for cycles can\n> > give results that differ from the programmable counter path.\n> >\n> > Extend the existing PMCCNTR avoidance decision from the SMT case to\n> > also cover Olympus. Store the result in the common arm_pmu state at\n> > registration time, so arm_pmuv3 can keep using a single flag when\n> > deciding whether CPU_CYCLES may use PMCCNTR_EL0.\n> >\n> > Use the cached MIDR from cpu_data to identify Olympus parts and avoid\n> > reading MIDR_EL1 in the event path.\n> >\n> > Signed-off-by: Besar Wicaksono \n> > ---\n> >\n> > Changes from v1:\n> > * add CONFIG_ARM64 check to fix build error found by kernel test robot\n> > * add explicit include of \n> > v1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-\n> bwicaksono@nvidia.com/\n> >\n> > Changes from v2:\n> > * Move the Olympus PMCCNTR avoidance check from arm_pmuv3.c to the\n> > common arm_pmu registration path.\n> > * Replace the PMUv3-only has_smt flag with avoid_pmccntr, covering both\n> > the existing SMT restriction and the Olympus MIDR restriction.\n> > * Use the cached per-CPU MIDR from cpu_data instead of calling\n> > is_midr_in_range_list() from armv8pmu_can_use_pmccntr().\n> > * Add the required asm/cpu.h include for cpu_data.\n> > * Drop the use_pmccntr override patch from this revision.\n> > v2: https://lore.kernel.org/linux-arm-kernel/20260421203856.3539186-1-\n> bwicaksono@nvidia.com/#t\n> >\n> > ---\n> > drivers/perf/arm_pmu.c | 78\n> +++++++++++++++++++++++++++++++++---\n> > drivers/perf/arm_pmuv3.c | 8 +---\n> > include/linux/perf/arm_pmu.h | 2 +-\n> > 3 files changed, 75 insertions(+), 13 deletions(-)\n> >\n> > diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c\n> > index 939bcbd433aa..7df185ee7b74 100644\n> > --- a/drivers/perf/arm_pmu.c\n> > +++ b/drivers/perf/arm_pmu.c\n> > @@ -24,6 +24,8 @@\n> > #include \n> > #include \n> >\n> > +#include \n> > +#include \n> > #include \n> >\n> > static int armpmu_count_irq_users(const struct cpumask *affinity,\n> > @@ -920,6 +922,76 @@ void armpmu_free(struct arm_pmu *pmu)\n> > kfree(pmu);\n> > }\n> >\n> > +#ifdef CONFIG_ARM64\n> > +/*\n> > + * List of CPUs that should avoid using PMCCNTR_EL0.\n> > + */\n> > +static struct midr_range armpmu_avoid_pmccntr_cpus[] = {\n> > + /*\n> > + * The PMCCNTR_EL0 in Olympus CPU may still increment while in\n> WFI/WFE state.\n> > + * This is an implementation specific behavior and not an erratum.\n> > + *\n> > + * From ARM DDI0487 D14.4:\n> > + * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR\n> count\n> > + * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n> > + *\n> > + * From ARM DDI0487 D24.5.2:\n> > + * All counters are subject to any changes in clock frequency, including\n> > + * clock stopping caused by the WFI and WFE instructions.\n> > + * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n> > + * PMCCNTR_EL0 continues to increment when clocks are stopped by\n> WFI and\n> > + * WFE instructions.\n> > + */\n> > + MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n> > + {}\n> > +};\n> > +\n> > +static bool armpmu_is_in_avoid_pmccntr_cpus(int cpu)\n> > +{\n> > + struct midr_range const *r = armpmu_avoid_pmccntr_cpus;\n> > + u32 midr = (u32)per_cpu(cpu_data, cpu).reg_midr;\n> \n> Hi Besar,\n> \n> This is still fragile to the thing I mentioned on V2 about some of the\n> CPUs not being online, then cpu_data isn't initialized for those CPUs.\n> \n> Sashiko suggests to use cpumask_any_and(&pmu->supported_cpus,\n> cpu_online_mask), and currently the Arm PMUs do require at least one CPU\n> online so it's probably fine. Although it could be fragile if we added\n> deferred probing in the future.\n> \n> The other alternative is to put this in __armv8pmu_probe_pmu(), although\n> then you end up with both arm_pmuv3 and arm_pmu initializing\n> cpu_pmu->has_smt, but I'm sure there is a way to make it fit somehow.\n> \n\nThanks for the pointers, James and Sashiko. I will try this alternative approach\nand add the check on __armv8pmu_probe_pmu(). I would still rename\nhas_smt to avoid_pmccntr and keep the SMT check on arm_pmu.c.\n\nRegards,\nBesar","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=pGBDoafc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14142-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"pGBDoafc\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.198.38","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6kbl58qVz1yJ0\n\tfor ; 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