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GET /api/patches/2227349/?format=api
{ "id": 2227349, "url": "http://patchwork.ozlabs.org/api/patches/2227349/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-3-0296bccb9f4e@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260423-glymur-v2-3-0296bccb9f4e@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-23T13:29:32", "name": "[v2,03/13] gpu: host1x: Migrate to generic dma context bus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cfeaeadb44f29d285ba0e4a7c5cb26c8c18fbacb", "submitter": { "id": 93161, "url": "http://patchwork.ozlabs.org/api/people/93161/?format=api", "name": "Vishnu Reddy", "email": "busanna.reddy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-3-0296bccb9f4e@oss.qualcomm.com/mbox/", "series": [ { "id": 501197, "url": "http://patchwork.ozlabs.org/api/series/501197/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197", "date": "2026-04-23T13:29:29", "name": "media: iris: Add support for glymur platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501197/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227349/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227349/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13920-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ghjhN4sM;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Nk6Qqv1a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260423-glymur-v2-3-0296bccb9f4e@oss.qualcomm.com>", "References": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "In-Reply-To": "<20260423-glymur-v2-0-0296bccb9f4e@oss.qualcomm.com>", "To": "Bryan O'Donoghue <bod@kernel.org>,\n Vikash Garodia <vikash.garodia@oss.qualcomm.com>,\n Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,\n Abhinav Kumar <abhinav.kumar@linux.dev>,\n Mauro Carvalho Chehab <mchehab@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Joerg Roedel <joro@8bytes.org>,\n Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Stefan Schmidt <stefan.schmidt@linaro.org>,\n Hans Verkuil <hverkuil@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n \"Rafael J. Wysocki\" <rafael@kernel.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Thierry Reding <thierry.reding@kernel.org>,\n Mikko Perttunen <mperttunen@nvidia.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Jonathan Hunter <jonathanh@nvidia.com>", "Cc": "linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy <busanna.reddy@oss.qualcomm.com>,\n Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776950985; l=9125;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=KAZGJcms8W81ZmK2zjFmjrcOZ1HBohJzHFPq/diKVJY=;\n b=G6RcIQ17RYpJWR8JDM591/LpwoVkQ6XZG36hL1jc+jg2eaqYSNxbMR/xAkW6nsA4aDE06Ugnh\n G6EQkaClw2AAJ756RAnNV8DDM78rg/FXf7UziboAh2VUdY6eWdWtwwA", "X-Developer-Key": "i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=", "X-Proofpoint-GUID": "HvIkcIZJIniEnTJ97ybyrmLCJE0fTOsF", "X-Proofpoint-ORIG-GUID": "HvIkcIZJIniEnTJ97ybyrmLCJE0fTOsF", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfX+EK02WoVNwfa\n Cz9YMCXpaiVuJkiRFhdDTTnHxbYG8/SyADhKWOmxIoF5fKuvqldxmKCR8F4+r0H42v4AOgkooYt\n D36bVUrC7xwDPZJ7unzCttYVzuaF6ew4YFSfKOhOO02YtSYH0cluT/UYElvk+0aVWGN7GyEjayy\n pLWZJqL1cpNNd0ZbCCl/abTfWJGN8GsgB0ileJwOaJbC4wKuQcAd7SU2ozSt4EW3Cj9b5FyQVll\n hTXO1j9pyGEvPjYYbPcy51S7saoKC23FDWrC9l0eeLhXjkxEBeekDLOLBIU2GKCdDgQ9TCkaO+J\n OckuNi/NMfTRW6AN8KjktIhUBtOIyN+EhDnXkARgdL56LhPdxHgnqQ5jHbHrxK8pG4yRyorJ44D\n /6JFCPHPFwF4Lw6mPd3nQy8leqq6dfmKftXlZD0/Oz7JDwA5/44ysZ7V50dphwQ2DUZcFX4j9I9\n K0YLH9h/CPzsZjybKJA==", "X-Authority-Analysis": "v=2.4 cv=ablRWxot c=1 sm=1 tr=0 ts=69ea1ef1 cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22\n a=EUspDBNiAAAA:8 a=smED1w4oCYVFD8D0vxMA:9 a=QEXdDO2ut3YA:10\n a=uG9DUKGECoFWVXl0Dc02:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 phishscore=0 priorityscore=1501 suspectscore=0 adultscore=0\n impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230134" }, "content": "From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>\n\nThe host1x driver creates context bank devices to map IOMMU contexts\nfor memory isolation. Previously, this required a host1x-specific bus\ntype with its own device setup and IOMMU configuration logic.\n\nA generic \"dma-context-bus\" is now available in the driver core that\nhandles this for any driver. Replace the host1x-specific bus with this\nshared generic bus. This removes the private bus registration, device\nsetup, and of_dma_configure_id() from host1x, as the generic bus handles\nall of this internally.\n\nThe IOMMU subsystem is also updated to reference the generic bus instead\nof the host1x-specific one.\n\nSigned-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>\nSigned-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>\n---\n drivers/gpu/drm/tegra/uapi.c | 2 +-\n drivers/gpu/host1x/Kconfig | 5 +---\n drivers/gpu/host1x/Makefile | 1 -\n drivers/gpu/host1x/context.c | 47 ++++++++++++--------------------------\n drivers/gpu/host1x/context.h | 3 +--\n drivers/gpu/host1x/context_bus.c | 26 ---------------------\n drivers/iommu/iommu.c | 6 ++---\n include/linux/host1x.h | 2 +-\n include/linux/host1x_context_bus.h | 15 ------------\n 9 files changed, 21 insertions(+), 86 deletions(-)", "diff": "diff --git a/drivers/gpu/drm/tegra/uapi.c b/drivers/gpu/drm/tegra/uapi.c\nindex c0ac6b45f2d7..9547725a6c3c 100644\n--- a/drivers/gpu/drm/tegra/uapi.c\n+++ b/drivers/gpu/drm/tegra/uapi.c\n@@ -215,7 +215,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f\n \tkref_init(&mapping->ref);\n \n \tif (context->memory_context)\n-\t\tmapping_dev = &context->memory_context->dev;\n+\t\tmapping_dev = context->memory_context->dev;\n \telse\n \t\tmapping_dev = context->client->base.dev;\n \ndiff --git a/drivers/gpu/host1x/Kconfig b/drivers/gpu/host1x/Kconfig\nindex e6c78ae2003a..0539ff057a51 100644\n--- a/drivers/gpu/host1x/Kconfig\n+++ b/drivers/gpu/host1x/Kconfig\n@@ -1,13 +1,10 @@\n # SPDX-License-Identifier: GPL-2.0-only\n \n-config TEGRA_HOST1X_CONTEXT_BUS\n-\tbool\n-\n config TEGRA_HOST1X\n \ttristate \"NVIDIA Tegra host1x driver\"\n \tdepends on ARCH_TEGRA || COMPILE_TEST\n \tselect DMA_SHARED_BUFFER\n-\tselect TEGRA_HOST1X_CONTEXT_BUS\n+\tselect DMA_CONTEXT_BUS\n \tselect IOMMU_IOVA\n \thelp\n \t Driver for the NVIDIA Tegra host1x hardware.\ndiff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile\nindex fead483af0b4..2ccd9a5f1c65 100644\n--- a/drivers/gpu/host1x/Makefile\n+++ b/drivers/gpu/host1x/Makefile\n@@ -23,4 +23,3 @@ host1x-$(CONFIG_IOMMU_API) += \\\n \tcontext.o\n \n obj-$(CONFIG_TEGRA_HOST1X) += host1x.o\n-obj-$(CONFIG_TEGRA_HOST1X_CONTEXT_BUS) += context_bus.o\ndiff --git a/drivers/gpu/host1x/context.c b/drivers/gpu/host1x/context.c\nindex d50d41c20561..ab7b156ab002 100644\n--- a/drivers/gpu/host1x/context.c\n+++ b/drivers/gpu/host1x/context.c\n@@ -13,16 +13,12 @@\n #include \"context.h\"\n #include \"dev.h\"\n \n-static void host1x_memory_context_release(struct device *dev)\n-{\n-\t/* context device is freed in host1x_memory_context_list_free() */\n-}\n-\n int host1x_memory_context_list_init(struct host1x *host1x)\n {\n \tstruct host1x_memory_context_list *cdl = &host1x->context_list;\n \tstruct device_node *node = host1x->dev->of_node;\n \tstruct host1x_memory_context *ctx;\n+\tstruct device *dev;\n \tunsigned int i;\n \tint err;\n \n@@ -44,42 +40,27 @@ int host1x_memory_context_list_init(struct host1x *host1x)\n \n \t\tctx->host = host1x;\n \n-\t\tdevice_initialize(&ctx->dev);\n-\n \t\t/*\n \t\t * Due to an issue with T194 NVENC, only 38 bits can be used.\n \t\t * Anyway, 256GiB of IOVA ought to be enough for anyone.\n \t\t */\n \t\tctx->dma_mask = DMA_BIT_MASK(38);\n-\t\tctx->dev.dma_mask = &ctx->dma_mask;\n-\t\tctx->dev.coherent_dma_mask = ctx->dma_mask;\n-\t\tdev_set_name(&ctx->dev, \"host1x-ctx.%d\", i);\n-\t\tctx->dev.bus = &host1x_context_device_bus_type;\n-\t\tctx->dev.parent = host1x->dev;\n-\t\tctx->dev.release = host1x_memory_context_release;\n-\n-\t\tctx->dev.dma_parms = &ctx->dma_parms;\n-\t\tdma_set_max_seg_size(&ctx->dev, UINT_MAX);\n-\n-\t\terr = device_add(&ctx->dev);\n-\t\tif (err) {\n+\n+\t\tdev = create_dma_context_bus_device(host1x->dev, NULL, ctx->dma_mask, &i);\n+\t\tif (IS_ERR(dev)) {\n+\t\t\terr = PTR_ERR(dev);\n \t\t\tdev_err(host1x->dev, \"could not add context device %d: %d\\n\", i, err);\n-\t\t\tput_device(&ctx->dev);\n \t\t\tgoto unreg_devices;\n \t\t}\n \n-\t\terr = of_dma_configure_id(&ctx->dev, node, true, &i);\n-\t\tif (err) {\n-\t\t\tdev_err(host1x->dev, \"IOMMU configuration failed for context device %d: %d\\n\",\n-\t\t\t\ti, err);\n-\t\t\tdevice_unregister(&ctx->dev);\n-\t\t\tgoto unreg_devices;\n-\t\t}\n+\t\tctx->dev = dev;\n+\t\tctx->dev->dma_parms = &ctx->dma_parms;\n+\t\tdma_set_max_seg_size(ctx->dev, UINT_MAX);\n \n-\t\tif (!tegra_dev_iommu_get_stream_id(&ctx->dev, &ctx->stream_id) ||\n-\t\t !device_iommu_mapped(&ctx->dev)) {\n+\t\tif (!tegra_dev_iommu_get_stream_id(ctx->dev, &ctx->stream_id) ||\n+\t\t !device_iommu_mapped(ctx->dev)) {\n \t\t\tdev_err(host1x->dev, \"Context device %d has no IOMMU!\\n\", i);\n-\t\t\tdevice_unregister(&ctx->dev);\n+\t\t\tdevice_unregister(ctx->dev);\n \n \t\t\t/*\n \t\t\t * This means that if IOMMU is disabled but context devices\n@@ -96,7 +77,7 @@ int host1x_memory_context_list_init(struct host1x *host1x)\n \n unreg_devices:\n \twhile (i--)\n-\t\tdevice_unregister(&cdl->devs[i].dev);\n+\t\tdevice_unregister(cdl->devs[i].dev);\n \n \tkfree(cdl->devs);\n \tcdl->devs = NULL;\n@@ -110,7 +91,7 @@ void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)\n \tunsigned int i;\n \n \tfor (i = 0; i < cdl->len; i++)\n-\t\tdevice_unregister(&cdl->devs[i].dev);\n+\t\tdevice_unregister(cdl->devs[i].dev);\n \n \tkfree(cdl->devs);\n \tcdl->len = 0;\n@@ -132,7 +113,7 @@ struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,\n \tfor (i = 0; i < cdl->len; i++) {\n \t\tstruct host1x_memory_context *cd = &cdl->devs[i];\n \n-\t\tif (cd->dev.iommu->iommu_dev != dev->iommu->iommu_dev)\n+\t\tif (cd->dev->iommu->iommu_dev != dev->iommu->iommu_dev)\n \t\t\tcontinue;\n \n \t\tif (cd->owner == pid) {\ndiff --git a/drivers/gpu/host1x/context.h b/drivers/gpu/host1x/context.h\nindex 3e03bc1d3bac..558638c457d6 100644\n--- a/drivers/gpu/host1x/context.h\n+++ b/drivers/gpu/host1x/context.h\n@@ -8,13 +8,12 @@\n #ifndef __HOST1X_CONTEXT_H\n #define __HOST1X_CONTEXT_H\n \n+#include <linux/dma_context_bus.h>\n #include <linux/mutex.h>\n #include <linux/refcount.h>\n \n struct host1x;\n \n-extern struct bus_type host1x_context_device_bus_type;\n-\n struct host1x_memory_context_list {\n \tstruct mutex lock;\n \tstruct host1x_memory_context *devs;\ndiff --git a/drivers/gpu/host1x/context_bus.c b/drivers/gpu/host1x/context_bus.c\ndeleted file mode 100644\nindex 7cd0e1a5edd1..000000000000\n--- a/drivers/gpu/host1x/context_bus.c\n+++ /dev/null\n@@ -1,26 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (c) 2021, NVIDIA Corporation.\n- */\n-\n-#include <linux/device.h>\n-#include <linux/of.h>\n-\n-const struct bus_type host1x_context_device_bus_type = {\n-\t.name = \"host1x-context\",\n-};\n-EXPORT_SYMBOL_GPL(host1x_context_device_bus_type);\n-\n-static int __init host1x_context_device_bus_init(void)\n-{\n-\tint err;\n-\n-\terr = bus_register(&host1x_context_device_bus_type);\n-\tif (err < 0) {\n-\t\tpr_err(\"bus type registration failed: %d\\n\", err);\n-\t\treturn err;\n-\t}\n-\n-\treturn 0;\n-}\n-postcore_initcall(host1x_context_device_bus_init);\ndiff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c\nindex 61c12ba78206..5d0fad1402eb 100644\n--- a/drivers/iommu/iommu.c\n+++ b/drivers/iommu/iommu.c\n@@ -16,7 +16,7 @@\n #include <linux/export.h>\n #include <linux/slab.h>\n #include <linux/errno.h>\n-#include <linux/host1x_context_bus.h>\n+#include <linux/dma_context_bus.h>\n #include <linux/iommu.h>\n #include <linux/iommufd.h>\n #include <linux/idr.h>\n@@ -173,8 +173,8 @@ static const struct bus_type * const iommu_buses[] = {\n #ifdef CONFIG_FSL_MC_BUS\n \t&fsl_mc_bus_type,\n #endif\n-#ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS\n-\t&host1x_context_device_bus_type,\n+#ifdef CONFIG_DMA_CONTEXT_BUS\n+\t&dma_context_bus_type,\n #endif\n #ifdef CONFIG_CDX_BUS\n \t&cdx_bus_type,\ndiff --git a/include/linux/host1x.h b/include/linux/host1x.h\nindex 1f5f55917d1c..30dbb3a71828 100644\n--- a/include/linux/host1x.h\n+++ b/include/linux/host1x.h\n@@ -462,7 +462,7 @@ struct host1x_memory_context {\n \tstruct pid *owner;\n \n \tstruct device_dma_parameters dma_parms;\n-\tstruct device dev;\n+\tstruct device *dev;\n \tu64 dma_mask;\n \tu32 stream_id;\n };\ndiff --git a/include/linux/host1x_context_bus.h b/include/linux/host1x_context_bus.h\ndeleted file mode 100644\nindex c928cb432680..000000000000\n--- a/include/linux/host1x_context_bus.h\n+++ /dev/null\n@@ -1,15 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-or-later */\n-/*\n- * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.\n- */\n-\n-#ifndef __LINUX_HOST1X_CONTEXT_BUS_H\n-#define __LINUX_HOST1X_CONTEXT_BUS_H\n-\n-#include <linux/device.h>\n-\n-#ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS\n-extern const struct bus_type host1x_context_device_bus_type;\n-#endif\n-\n-#endif\n", "prefixes": [ "v2", "03/13" ] }