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GET /api/patches/2225565/?format=api
{ "id": 2225565, "url": "http://patchwork.ozlabs.org/api/patches/2225565/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074940.2916287-1-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421074940.2916287-1-frank.chang@sifive.com>", "list_archive_url": null, "date": "2026-04-21T07:49:40", "name": "[v2] target/riscv: Mask xepc[0] only when Zc* extension is enabled", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2f89054f52539f1dc81a6a3c406078c469faa0d0", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074940.2916287-1-frank.chang@sifive.com/mbox/", "series": [ { "id": 500752, "url": "http://patchwork.ozlabs.org/api/series/500752/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500752", "date": "2026-04-21T07:49:40", "name": "[v2] target/riscv: Mask xepc[0] only when Zc* extension is enabled", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500752/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225565/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225565/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=hY+ON+UM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x633.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nIALIGN is 16 when the CPU supports the Zc* extension. Only xepc[0]\nshould be masked when the Zc* extension is enabled.\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\n---\n target/riscv/internals.h | 12 +++++++++---\n 1 file changed, 9 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex b001cbc080a..ab8dea45c90 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -173,9 +173,15 @@ static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)\n \n static inline target_ulong get_xepc_mask(CPURISCVState *env)\n {\n- /* When IALIGN=32, both low bits must be zero.\n- * When IALIGN=16 (has C extension), only bit 0 must be zero. */\n- if (riscv_has_ext(env, RVC)) {\n+ RISCVCPU *cpu = env_archcpu(env);\n+\n+ /*\n+ * When IALIGN=32, both low bits must be zero.\n+ * When IALIGN=16 (has C or Zc* extensions), only bit 0 must be zero.\n+ */\n+ if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca ||\n+ cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce ||\n+ cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) {\n return ~(target_ulong)1;\n } else {\n return ~(target_ulong)3;\n", "prefixes": [ "v2" ] }