[{"id":3680141,"web_url":"http://patchwork.ozlabs.org/comment/3680141/","msgid":"","list_archive_url":null,"date":"2026-04-21T23:57:10","subject":"Re: [PATCH v2] target/riscv: Mask xepc[0] only when Zc* extension is\n enabled","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:50 PM wrote:\n>\n> From: Frank Chang \n>\n> IALIGN is 16 when the CPU supports the Zc* extension. Only xepc[0]\n> should be masked when the Zc* extension is enabled.\n>\n> Signed-off-by: Frank Chang \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/internals.h | 12 +++++++++---\n> 1 file changed, 9 insertions(+), 3 deletions(-)\n>\n> diff --git a/target/riscv/internals.h b/target/riscv/internals.h\n> index b001cbc080a..ab8dea45c90 100644\n> --- a/target/riscv/internals.h\n> +++ b/target/riscv/internals.h\n> @@ -173,9 +173,15 @@ static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)\n>\n> static inline target_ulong get_xepc_mask(CPURISCVState *env)\n> {\n> - /* When IALIGN=32, both low bits must be zero.\n> - * When IALIGN=16 (has C extension), only bit 0 must be zero. */\n> - if (riscv_has_ext(env, RVC)) {\n> + RISCVCPU *cpu = env_archcpu(env);\n> +\n> + /*\n> + * When IALIGN=32, both low bits must be zero.\n> + * When IALIGN=16 (has C or Zc* extensions), only bit 0 must be zero.\n> + */\n> + if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca ||\n> + cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce ||\n> + cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) {\n> return ~(target_ulong)1;\n> } else {\n> return ~(target_ulong)3;\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=FC4iLYUB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 21 Apr 2026\n 16:57:38 -0700 (PDT)","MIME-Version":"1.0","References":"<20260421074940.2916287-1-frank.chang@sifive.com>","In-Reply-To":"<20260421074940.2916287-1-frank.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 22 Apr 2026 09:57:10 +1000","X-Gm-Features":"AQROBzBHs5KgDJc1ZLdsdOp1k94OSWHIEnhy9m26XKLAAPNsm5Ajgc9LMnO55iE","Message-ID":"\n ","Subject":"Re: [PATCH v2] target/riscv: Mask xepc[0] only when Zc* extension is\n enabled","To":"frank.chang@sifive.com","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::533;\n envelope-from=alistair23@gmail.com; helo=mail-ed1-x533.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680143,"web_url":"http://patchwork.ozlabs.org/comment/3680143/","msgid":"","list_archive_url":null,"date":"2026-04-21T23:59:30","subject":"Re: [PATCH v2] target/riscv: Mask xepc[0] only when Zc* extension is\n enabled","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:50 PM wrote:\n>\n> From: Frank Chang \n>\n> IALIGN is 16 when the CPU supports the Zc* extension. Only xepc[0]\n> should be masked when the Zc* extension is enabled.\n>\n> Signed-off-by: Frank Chang \n\nThanks!\n\nApplied to riscv-to-apply.next\n\nAlistair\n\n> ---\n> target/riscv/internals.h | 12 +++++++++---\n> 1 file changed, 9 insertions(+), 3 deletions(-)\n>\n> diff --git a/target/riscv/internals.h b/target/riscv/internals.h\n> index b001cbc080a..ab8dea45c90 100644\n> --- a/target/riscv/internals.h\n> +++ b/target/riscv/internals.h\n> @@ -173,9 +173,15 @@ static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)\n>\n> static inline target_ulong get_xepc_mask(CPURISCVState *env)\n> {\n> - /* When IALIGN=32, both low bits must be zero.\n> - * When IALIGN=16 (has C extension), only bit 0 must be zero. */\n> - if (riscv_has_ext(env, RVC)) {\n> + RISCVCPU *cpu = env_archcpu(env);\n> +\n> + /*\n> + * When IALIGN=32, both low bits must be zero.\n> + * When IALIGN=16 (has C or Zc* extensions), only bit 0 must be zero.\n> + */\n> + if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca ||\n> + cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce ||\n> + cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) {\n> return ~(target_ulong)1;\n> } else {\n> return ~(target_ulong)3;\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=gEw4ejL9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 21 Apr 2026\n 16:59:56 -0700 (PDT)","MIME-Version":"1.0","References":"<20260421074940.2916287-1-frank.chang@sifive.com>","In-Reply-To":"<20260421074940.2916287-1-frank.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 22 Apr 2026 09:59:30 +1000","X-Gm-Features":"AQROBzAOcbtffRYvwFrVU0qsiEZBH_-0Q2t2DAgGCUwbojcBjCbTkFq0egOHYYA","Message-ID":"\n ","Subject":"Re: [PATCH v2] target/riscv: Mask xepc[0] only when Zc* extension is\n enabled","To":"frank.chang@sifive.com","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::631;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x631.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]