Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2225548/?format=api
{ "id": 2225548, "url": "http://patchwork.ozlabs.org/api/patches/2225548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421071107.2848439-1-frank.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421071107.2848439-1-frank.chang@sifive.com>", "list_archive_url": null, "date": "2026-04-21T07:11:07", "name": "[v3] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "729c0f4c7867151a2c99ffe6669baf0900491c69", "submitter": { "id": 79604, "url": "http://patchwork.ozlabs.org/api/people/79604/?format=api", "name": "Frank Chang", "email": "frank.chang@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421071107.2848439-1-frank.chang@sifive.com/mbox/", "series": [ { "id": 500746, "url": "http://patchwork.ozlabs.org/api/series/500746/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500746", "date": "2026-04-21T07:11:07", "name": "[v3] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500746/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225548/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225548/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=gg8LFrYR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0D7j129Yz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 17:12:15 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF5GV-0003dt-RK; Tue, 21 Apr 2026 03:11:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)\n id 1wF5GS-0003dR-9W\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 03:11:20 -0400", "from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)\n id 1wF5GP-00044B-Sy\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 03:11:20 -0400", "by mail-pj1-x1033.google.com with SMTP id\n 98e67ed59e1d1-362bb3260f1so260005a91.2\n for <qemu-devel@nongnu.org>; Tue, 21 Apr 2026 00:11:16 -0700 (PDT)", "from hsinchu16.internal.sifive.com ([210.176.154.34])\n by smtp.gmail.com with ESMTPSA id\n 41be03b00d2f7-c7976f9cacasm10674709a12.8.2026.04.21.00.11.11\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 21 Apr 2026 00:11:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1776755475; x=1777360275; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=1ffO50MMxG2IDWSSIbiX+9kzNZ5vhwSUgSE0rk877XE=;\n b=gg8LFrYR9ZI3LCETgkkhUQcq0TzF9NaZvmB3Wx7pTCiBQyqosb1FWQwHEkrNIn6CyD\n O+LnGGsXmj5DIhxL/ZKmcPl6r03qjltwdNr042Z5iHh79gZ0eHmBhJinuaPgF8c7LAVt\n Mna6M4nrPMd4lJLBNnGObf09BtQ4ap8XzwtlJFPEgr5wbYlEG7eEYoTLYvGdbtSMz+q0\n usA3zNa9OruL7gJgEMlywP2zVHGVcT+wRUBuuTz/U6K5MwBuX4cUCdCowFYf4jq3PzZH\n rWd5wAqi0NhwcoeC3yZFMVOOCDaY+o7EmHWJYc5HjnXO5S9X0xnPP+td9LjCkLKjwF4+\n eg+A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776755475; x=1777360275;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=1ffO50MMxG2IDWSSIbiX+9kzNZ5vhwSUgSE0rk877XE=;\n b=GFYz39PfawyEpJei/oE2SAevFuxy2cQqw2wmwO0LuxrlQmjtLe5q/zXVdSf1VX0z2Q\n Y12ovGxIPbmq6F17+qWXvukT5uMy1wolr23KOxh/TV6GHntw4RJK0/eyFdtqlvI0C9zc\n Q0MEkdn5JeXfRQxd0K4ZueAxQKSxQkldhbV/wswYYzS9yk5K3GsWGuH8CMqWsNicak1V\n GpaEusndqNn/lfMLcvlc+7Amt1LQPPzfl8dS8SrYEpKkEHvBUjqzTQBORiyiSA0dOKUc\n H1pOrn6EgfDAcHDP4h1Thwc0DFBg5QDkWFu0q8U9RH7tFi2Y+D/t8wS2y3dMM4c/m0sb\n pwrQ==", "X-Gm-Message-State": "AOJu0YykvvcJDxbab7+JEZ0czxzu8ooG4JTq6G+xAWi8WLl0jo+77GJm\n QPYfqN58AqOjqzJLjJL40e+CmJhAZIcmecW4T7nkW63/UlAW70JoBI7h5VxLmCaWqZcrQqBbnsp\n OP1qs4FyYlE9pVOwK9pyDAI+Uv0yzTnLxnJ8ZPTMl/InzTdXy2p/mbkbtOd2eVmdwlXj46iPOPo\n ZSuB5FSlkEZ7obGCyVzVIRKa61PQN/4zbMtwQPXFZQ19UqfVW8", "X-Gm-Gg": "AeBDievWrtpF/2su4Da0ic7VBh6Ah8pgMjRQdPm4gVrWCHRYmlbilEDXJ7gdEi2xFSB\n Jf4DrBN4fLFfbxhZQGHezpqZ8w7tQFdmwUHjQr2OuYHdAX94T04qZXkmfNHxkJMG9UzQ5+SMPJR\n XL+vB5hYi7sbEx4KdbgSdmz+PWkWdPhAcj+XcTwJHnOdoD+eeXZ74eNGx9Z59FbkmPJ3h5mZkG7\n 1IufW/dkw/a4sB4Jb3WEMwrXG5uY4gCM8L5+uhkBr58FBNKzTnBANIpbsMjh32RbKqCMfH7tlHF\n iZsJVF4Bbn3s1oBbXCfJrQEO2LhWotqy9zplSWoHFiFezxiHdgOMfm08R3CKT0f8HgEoDfqm24N\n eW0BVjoDH67vAJ0VQIw/1wZBCGew/NTSTJn2iNpaDUJqQBPiUz+1lMbXFST3ko7yz1uXp4wXq4t\n PZC7mwKopoja+h+fmGZ+OIApXcGjnCvuod5+r68O44HwtWD7U7cmUzTSx+SqVE", "X-Received": "by 2002:a17:90b:3950:b0:35f:b714:e516 with SMTP id\n 98e67ed59e1d1-361404659e2mr16246064a91.16.1776755474983;\n Tue, 21 Apr 2026 00:11:14 -0700 (PDT)", "From": "frank.chang@sifive.com", "To": "qemu-devel@nongnu.org", "Cc": "Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),\n Frank Chang <frank.chang@sifive.com>, Max Chou <max.chou@sifive.com>,\n Nutty Liu <nutty.liu@hotmail.com>,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Subject": "[PATCH v3] target/riscv: Initialize riscv_excp_names[] and\n riscv_intr_names[] using designated initializer", "Date": "Tue, 21 Apr 2026 15:11:07 +0800", "Message-ID": "<20260421071107.2848439-1-frank.chang@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1033;\n envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nUse designated initializers to initialize riscv_excp_names[] and\nriscv_intr_names[] so that we don't have to explicitly add \"reserved\"\nitems. Also, add the missing trap names: sw_check, hw_error,\nvirt_illegal_instruction, semihost, s_guest_external, and\ncounter_overflow.\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Max Chou <max.chou@sifive.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------\n 1 file changed, 45 insertions(+), 44 deletions(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f14..ce15a17c37d 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -328,60 +328,61 @@ const char * const riscv_rvv_regnames[] = {\n };\n \n static const char * const riscv_excp_names[] = {\n- \"misaligned_fetch\",\n- \"fault_fetch\",\n- \"illegal_instruction\",\n- \"breakpoint\",\n- \"misaligned_load\",\n- \"fault_load\",\n- \"misaligned_store\",\n- \"fault_store\",\n- \"user_ecall\",\n- \"supervisor_ecall\",\n- \"hypervisor_ecall\",\n- \"machine_ecall\",\n- \"exec_page_fault\",\n- \"load_page_fault\",\n- \"reserved\",\n- \"store_page_fault\",\n- \"double_trap\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\",\n- \"guest_exec_page_fault\",\n- \"guest_load_page_fault\",\n- \"reserved\",\n- \"guest_store_page_fault\",\n+ [RISCV_EXCP_INST_ADDR_MIS] = \"misaligned_fetch\",\n+ [RISCV_EXCP_INST_ACCESS_FAULT] = \"fault_fetch\",\n+ [RISCV_EXCP_ILLEGAL_INST] = \"illegal_instruction\",\n+ [RISCV_EXCP_BREAKPOINT] = \"breakpoint\",\n+ [RISCV_EXCP_LOAD_ADDR_MIS] = \"misaligned_load\",\n+ [RISCV_EXCP_LOAD_ACCESS_FAULT] = \"fault_load\",\n+ [RISCV_EXCP_STORE_AMO_ADDR_MIS] = \"misaligned_store\",\n+ [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = \"fault_store\",\n+ [RISCV_EXCP_U_ECALL] = \"user_ecall\",\n+ [RISCV_EXCP_S_ECALL] = \"supervisor_ecall\",\n+ [RISCV_EXCP_VS_ECALL] = \"hypervisor_ecall\",\n+ [RISCV_EXCP_M_ECALL] = \"machine_ecall\",\n+ [RISCV_EXCP_INST_PAGE_FAULT] = \"exec_page_fault\",\n+ [RISCV_EXCP_LOAD_PAGE_FAULT] = \"load_page_fault\",\n+ [RISCV_EXCP_STORE_PAGE_FAULT] = \"store_page_fault\",\n+ [RISCV_EXCP_DOUBLE_TRAP] = \"double_trap\",\n+ [RISCV_EXCP_SW_CHECK] = \"sw_check\",\n+ [RISCV_EXCP_HW_ERR] = \"hw_error\",\n+ [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = \"guest_exec_page_fault\",\n+ [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = \"guest_load_page_fault\",\n+ [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = \"virt_illegal_instruction\",\n+ [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = \"guest_store_page_fault\",\n+ [RISCV_EXCP_SEMIHOST] = \"semihost\",\n };\n \n static const char * const riscv_intr_names[] = {\n- \"u_software\",\n- \"s_software\",\n- \"vs_software\",\n- \"m_software\",\n- \"u_timer\",\n- \"s_timer\",\n- \"vs_timer\",\n- \"m_timer\",\n- \"u_external\",\n- \"s_external\",\n- \"vs_external\",\n- \"m_external\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\"\n+ [IRQ_U_SOFT] = \"u_software\",\n+ [IRQ_S_SOFT] = \"s_software\",\n+ [IRQ_VS_SOFT] = \"vs_software\",\n+ [IRQ_M_SOFT] = \"m_software\",\n+ [IRQ_U_TIMER] = \"u_timer\",\n+ [IRQ_S_TIMER] = \"s_timer\",\n+ [IRQ_VS_TIMER] = \"vs_timer\",\n+ [IRQ_M_TIMER] = \"m_timer\",\n+ [IRQ_U_EXT] = \"u_external\",\n+ [IRQ_S_EXT] = \"s_external\",\n+ [IRQ_VS_EXT] = \"vs_external\",\n+ [IRQ_M_EXT] = \"m_external\",\n+ [IRQ_S_GEXT] = \"s_guest_external\",\n+ [IRQ_PMU_OVF] = \"counter_overflow\",\n };\n \n const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)\n {\n if (async) {\n- return (cause < ARRAY_SIZE(riscv_intr_names)) ?\n- riscv_intr_names[cause] : \"(unknown)\";\n+ if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {\n+ return riscv_intr_names[cause];\n+ }\n } else {\n- return (cause < ARRAY_SIZE(riscv_excp_names)) ?\n- riscv_excp_names[cause] : \"(unknown)\";\n+ if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {\n+ return riscv_excp_names[cause];\n+ }\n }\n+\n+ return \"(unknown)\";\n }\n \n void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)\n", "prefixes": [ "v3" ] }