[{"id":3680138,"web_url":"http://patchwork.ozlabs.org/comment/3680138/","msgid":"","list_archive_url":null,"date":"2026-04-21T23:42:18","subject":"Re: [PATCH v3] target/riscv: Initialize riscv_excp_names[] and\n riscv_intr_names[] using designated initializer","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:13 PM wrote:\n>\n> From: Frank Chang \n>\n> Use designated initializers to initialize riscv_excp_names[] and\n> riscv_intr_names[] so that we don't have to explicitly add \"reserved\"\n> items. Also, add the missing trap names: sw_check, hw_error,\n> virt_illegal_instruction, semihost, s_guest_external, and\n> counter_overflow.\n>\n> Signed-off-by: Frank Chang \n> Reviewed-by: Max Chou \n> Reviewed-by: Daniel Henrique Barboza \n> Reviewed-by: Nutty Liu \n> Reviewed-by: Philippe Mathieu-Daudé \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------\n> 1 file changed, 45 insertions(+), 44 deletions(-)\n>\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 72c6f4f0f14..ce15a17c37d 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -328,60 +328,61 @@ const char * const riscv_rvv_regnames[] = {\n> };\n>\n> static const char * const riscv_excp_names[] = {\n> - \"misaligned_fetch\",\n> - \"fault_fetch\",\n> - \"illegal_instruction\",\n> - \"breakpoint\",\n> - \"misaligned_load\",\n> - \"fault_load\",\n> - \"misaligned_store\",\n> - \"fault_store\",\n> - \"user_ecall\",\n> - \"supervisor_ecall\",\n> - \"hypervisor_ecall\",\n> - \"machine_ecall\",\n> - \"exec_page_fault\",\n> - \"load_page_fault\",\n> - \"reserved\",\n> - \"store_page_fault\",\n> - \"double_trap\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"guest_exec_page_fault\",\n> - \"guest_load_page_fault\",\n> - \"reserved\",\n> - \"guest_store_page_fault\",\n> + [RISCV_EXCP_INST_ADDR_MIS] = \"misaligned_fetch\",\n> + [RISCV_EXCP_INST_ACCESS_FAULT] = \"fault_fetch\",\n> + [RISCV_EXCP_ILLEGAL_INST] = \"illegal_instruction\",\n> + [RISCV_EXCP_BREAKPOINT] = \"breakpoint\",\n> + [RISCV_EXCP_LOAD_ADDR_MIS] = \"misaligned_load\",\n> + [RISCV_EXCP_LOAD_ACCESS_FAULT] = \"fault_load\",\n> + [RISCV_EXCP_STORE_AMO_ADDR_MIS] = \"misaligned_store\",\n> + [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = \"fault_store\",\n> + [RISCV_EXCP_U_ECALL] = \"user_ecall\",\n> + [RISCV_EXCP_S_ECALL] = \"supervisor_ecall\",\n> + [RISCV_EXCP_VS_ECALL] = \"hypervisor_ecall\",\n> + [RISCV_EXCP_M_ECALL] = \"machine_ecall\",\n> + [RISCV_EXCP_INST_PAGE_FAULT] = \"exec_page_fault\",\n> + [RISCV_EXCP_LOAD_PAGE_FAULT] = \"load_page_fault\",\n> + [RISCV_EXCP_STORE_PAGE_FAULT] = \"store_page_fault\",\n> + [RISCV_EXCP_DOUBLE_TRAP] = \"double_trap\",\n> + [RISCV_EXCP_SW_CHECK] = \"sw_check\",\n> + [RISCV_EXCP_HW_ERR] = \"hw_error\",\n> + [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = \"guest_exec_page_fault\",\n> + [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = \"guest_load_page_fault\",\n> + [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = \"virt_illegal_instruction\",\n> + [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = \"guest_store_page_fault\",\n> + [RISCV_EXCP_SEMIHOST] = \"semihost\",\n> };\n>\n> static const char * const riscv_intr_names[] = {\n> - \"u_software\",\n> - \"s_software\",\n> - \"vs_software\",\n> - \"m_software\",\n> - \"u_timer\",\n> - \"s_timer\",\n> - \"vs_timer\",\n> - \"m_timer\",\n> - \"u_external\",\n> - \"s_external\",\n> - \"vs_external\",\n> - \"m_external\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\"\n> + [IRQ_U_SOFT] = \"u_software\",\n> + [IRQ_S_SOFT] = \"s_software\",\n> + [IRQ_VS_SOFT] = \"vs_software\",\n> + [IRQ_M_SOFT] = \"m_software\",\n> + [IRQ_U_TIMER] = \"u_timer\",\n> + [IRQ_S_TIMER] = \"s_timer\",\n> + [IRQ_VS_TIMER] = \"vs_timer\",\n> + [IRQ_M_TIMER] = \"m_timer\",\n> + [IRQ_U_EXT] = \"u_external\",\n> + [IRQ_S_EXT] = \"s_external\",\n> + [IRQ_VS_EXT] = \"vs_external\",\n> + [IRQ_M_EXT] = \"m_external\",\n> + [IRQ_S_GEXT] = \"s_guest_external\",\n> + [IRQ_PMU_OVF] = \"counter_overflow\",\n> };\n>\n> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)\n> {\n> if (async) {\n> - return (cause < ARRAY_SIZE(riscv_intr_names)) ?\n> - riscv_intr_names[cause] : \"(unknown)\";\n> + if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {\n> + return riscv_intr_names[cause];\n> + }\n> } else {\n> - return (cause < ARRAY_SIZE(riscv_excp_names)) ?\n> - riscv_excp_names[cause] : \"(unknown)\";\n> + if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {\n> + return riscv_excp_names[cause];\n> + }\n> }\n> +\n> + return \"(unknown)\";\n> }\n>\n> void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=b/NOLL8d;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 21 Apr 2026\n 16:42:44 -0700 (PDT)","MIME-Version":"1.0","References":"<20260421071107.2848439-1-frank.chang@sifive.com>","In-Reply-To":"<20260421071107.2848439-1-frank.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 22 Apr 2026 09:42:18 +1000","X-Gm-Features":"AQROBzAZGAQ5k5eIl1bTD-53Zu5Wcx1rmyVLzC1oCM9tWVYuP881CwLqrpLl7Uc","Message-ID":"\n ","Subject":"Re: [PATCH v3] target/riscv: Initialize riscv_excp_names[] and\n riscv_intr_names[] using designated initializer","To":"frank.chang@sifive.com","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ,\n Max Chou , Nutty Liu ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::634;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x634.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680140,"web_url":"http://patchwork.ozlabs.org/comment/3680140/","msgid":"","list_archive_url":null,"date":"2026-04-21T23:55:58","subject":"Re: [PATCH v3] target/riscv: Initialize riscv_excp_names[] and\n riscv_intr_names[] using designated initializer","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:13 PM wrote:\n>\n> From: Frank Chang \n>\n> Use designated initializers to initialize riscv_excp_names[] and\n> riscv_intr_names[] so that we don't have to explicitly add \"reserved\"\n> items. Also, add the missing trap names: sw_check, hw_error,\n> virt_illegal_instruction, semihost, s_guest_external, and\n> counter_overflow.\n>\n> Signed-off-by: Frank Chang \n> Reviewed-by: Max Chou \n> Reviewed-by: Daniel Henrique Barboza \n> Reviewed-by: Nutty Liu \n> Reviewed-by: Philippe Mathieu-Daudé \n\nThanks!\n\nApplied to riscv-to-apply.next\n\nAlistair\n\n> ---\n> target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------\n> 1 file changed, 45 insertions(+), 44 deletions(-)\n>\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 72c6f4f0f14..ce15a17c37d 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -328,60 +328,61 @@ const char * const riscv_rvv_regnames[] = {\n> };\n>\n> static const char * const riscv_excp_names[] = {\n> - \"misaligned_fetch\",\n> - \"fault_fetch\",\n> - \"illegal_instruction\",\n> - \"breakpoint\",\n> - \"misaligned_load\",\n> - \"fault_load\",\n> - \"misaligned_store\",\n> - \"fault_store\",\n> - \"user_ecall\",\n> - \"supervisor_ecall\",\n> - \"hypervisor_ecall\",\n> - \"machine_ecall\",\n> - \"exec_page_fault\",\n> - \"load_page_fault\",\n> - \"reserved\",\n> - \"store_page_fault\",\n> - \"double_trap\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"guest_exec_page_fault\",\n> - \"guest_load_page_fault\",\n> - \"reserved\",\n> - \"guest_store_page_fault\",\n> + [RISCV_EXCP_INST_ADDR_MIS] = \"misaligned_fetch\",\n> + [RISCV_EXCP_INST_ACCESS_FAULT] = \"fault_fetch\",\n> + [RISCV_EXCP_ILLEGAL_INST] = \"illegal_instruction\",\n> + [RISCV_EXCP_BREAKPOINT] = \"breakpoint\",\n> + [RISCV_EXCP_LOAD_ADDR_MIS] = \"misaligned_load\",\n> + [RISCV_EXCP_LOAD_ACCESS_FAULT] = \"fault_load\",\n> + [RISCV_EXCP_STORE_AMO_ADDR_MIS] = \"misaligned_store\",\n> + [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = \"fault_store\",\n> + [RISCV_EXCP_U_ECALL] = \"user_ecall\",\n> + [RISCV_EXCP_S_ECALL] = \"supervisor_ecall\",\n> + [RISCV_EXCP_VS_ECALL] = \"hypervisor_ecall\",\n> + [RISCV_EXCP_M_ECALL] = \"machine_ecall\",\n> + [RISCV_EXCP_INST_PAGE_FAULT] = \"exec_page_fault\",\n> + [RISCV_EXCP_LOAD_PAGE_FAULT] = \"load_page_fault\",\n> + [RISCV_EXCP_STORE_PAGE_FAULT] = \"store_page_fault\",\n> + [RISCV_EXCP_DOUBLE_TRAP] = \"double_trap\",\n> + [RISCV_EXCP_SW_CHECK] = \"sw_check\",\n> + [RISCV_EXCP_HW_ERR] = \"hw_error\",\n> + [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = \"guest_exec_page_fault\",\n> + [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = \"guest_load_page_fault\",\n> + [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = \"virt_illegal_instruction\",\n> + [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = \"guest_store_page_fault\",\n> + [RISCV_EXCP_SEMIHOST] = \"semihost\",\n> };\n>\n> static const char * const riscv_intr_names[] = {\n> - \"u_software\",\n> - \"s_software\",\n> - \"vs_software\",\n> - \"m_software\",\n> - \"u_timer\",\n> - \"s_timer\",\n> - \"vs_timer\",\n> - \"m_timer\",\n> - \"u_external\",\n> - \"s_external\",\n> - \"vs_external\",\n> - \"m_external\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\",\n> - \"reserved\"\n> + [IRQ_U_SOFT] = \"u_software\",\n> + [IRQ_S_SOFT] = \"s_software\",\n> + [IRQ_VS_SOFT] = \"vs_software\",\n> + [IRQ_M_SOFT] = \"m_software\",\n> + [IRQ_U_TIMER] = \"u_timer\",\n> + [IRQ_S_TIMER] = \"s_timer\",\n> + [IRQ_VS_TIMER] = \"vs_timer\",\n> + [IRQ_M_TIMER] = \"m_timer\",\n> + [IRQ_U_EXT] = \"u_external\",\n> + [IRQ_S_EXT] = \"s_external\",\n> + [IRQ_VS_EXT] = \"vs_external\",\n> + [IRQ_M_EXT] = \"m_external\",\n> + [IRQ_S_GEXT] = \"s_guest_external\",\n> + [IRQ_PMU_OVF] = \"counter_overflow\",\n> };\n>\n> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)\n> {\n> if (async) {\n> - return (cause < ARRAY_SIZE(riscv_intr_names)) ?\n> - riscv_intr_names[cause] : \"(unknown)\";\n> + if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {\n> + return riscv_intr_names[cause];\n> + }\n> } else {\n> - return (cause < ARRAY_SIZE(riscv_excp_names)) ?\n> - riscv_excp_names[cause] : \"(unknown)\";\n> + if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {\n> + return riscv_excp_names[cause];\n> + }\n> }\n> +\n> + return \"(unknown)\";\n> }\n>\n> void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=p6jt9vbq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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