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GET /api/patches/2225501/?format=api
{ "id": 2225501, "url": "http://patchwork.ozlabs.org/api/patches/2225501/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-6-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421053140.752059-6-joel@jms.id.au>", "list_archive_url": null, "date": "2026-04-21T05:31:30", "name": "[v3,05/13] hw/riscv/virt: Move AIA initialisation to helper file", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0fa881c37df30ae19439bccaaf1b7861f322e69a", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-6-joel@jms.id.au/mbox/", "series": [ { "id": 500733, "url": "http://patchwork.ozlabs.org/api/series/500733/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733", "date": "2026-04-21T05:31:26", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500733/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225501/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225501/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=O0pTDuvJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09zK09tQz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:34:53 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3jn-0000Ui-W5; Tue, 21 Apr 2026 01:33:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3jm-0000Tw-5u\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:30 -0400", "from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3jk-0004Qp-1S\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:29 -0400", "by mail-pj1-x1032.google.com with SMTP id\n 98e67ed59e1d1-35f9ab079bdso2375591a91.2\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:33:27 -0700 (PDT)", "from donnager-debian.. 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Separate it\nout in order to share code with such systems.\n\nThe virt machine keeps machine specific #defines such as\nVIRT_IRQCHIP_NUM_MSIS, VIRT_IRQCHIP_NUM_PRIO_BITS.\n\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>\n---\nv3:\n - Add r-b\n - Move fewer things out of virt machine into aia common code, as they\n are virt machine specific and not part of aia. Done as part of this\n movement patch to avoid moving them out only put them back in the\n next patch.\n---\n hw/riscv/aia.h | 26 +++++++++++\n include/hw/riscv/virt.h | 1 -\n hw/riscv/aia.c | 89 ++++++++++++++++++++++++++++++++++++++\n hw/riscv/virt-acpi-build.c | 2 +\n hw/riscv/virt.c | 87 +++++--------------------------------\n hw/riscv/meson.build | 2 +-\n 6 files changed, 129 insertions(+), 78 deletions(-)\n create mode 100644 hw/riscv/aia.h\n create mode 100644 hw/riscv/aia.c", "diff": "diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h\nnew file mode 100644\nindex 000000000000..dbb833340276\n--- /dev/null\n+++ b/hw/riscv/aia.h\n@@ -0,0 +1,26 @@\n+/*\n+ * QEMU RISC-V Advanced Interrupt Architecture (AIA)\n+ *\n+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_RISCV_AIA_H\n+#define HW_RISCV_AIA_H\n+\n+#include \"exec/hwaddr.h\"\n+\n+#define VIRT_IRQCHIP_NUM_SOURCES 96\n+\n+uint32_t imsic_num_bits(uint32_t count);\n+\n+DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n+ const MemMapEntry *aplic_m,\n+ const MemMapEntry *aplic_s,\n+ const MemMapEntry *imsic_m,\n+ const MemMapEntry *imsic_s,\n+ int socket, int base_hartid, int hart_count,\n+ uint32_t num_msis, uint32_t num_prio_bits);\n+\n+#endif\ndiff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h\nindex 18a2a323a344..ad858deb76ad 100644\n--- a/include/hw/riscv/virt.h\n+++ b/include/hw/riscv/virt.h\n@@ -135,7 +135,6 @@ enum {\n bool virt_is_acpi_enabled(RISCVVirtState *s);\n bool virt_is_iommu_sys_enabled(RISCVVirtState *s);\n void virt_acpi_setup(RISCVVirtState *vms);\n-uint32_t imsic_num_bits(uint32_t count);\n \n /*\n * The virt machine physical address space used by some of the devices\ndiff --git a/hw/riscv/aia.c b/hw/riscv/aia.c\nnew file mode 100644\nindex 000000000000..c724612a50a5\n--- /dev/null\n+++ b/hw/riscv/aia.c\n@@ -0,0 +1,89 @@\n+/*\n+ * QEMU RISC-V Advanced Interrupt Architecture (AIA)\n+ *\n+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"system/kvm.h\"\n+#include \"hw/intc/riscv_aplic.h\"\n+#include \"hw/intc/riscv_imsic.h\"\n+\n+#include \"aia.h\"\n+\n+uint32_t imsic_num_bits(uint32_t count)\n+{\n+ uint32_t ret = 0;\n+\n+ while (BIT(ret) < count) {\n+ ret++;\n+ }\n+\n+ return ret;\n+}\n+\n+DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n+ const MemMapEntry *aplic_m,\n+ const MemMapEntry *aplic_s,\n+ const MemMapEntry *imsic_m,\n+ const MemMapEntry *imsic_s,\n+ int socket, int base_hartid, int hart_count,\n+ uint32_t num_msis, uint32_t num_prio_bits)\n+{\n+ int i;\n+ hwaddr addr = 0;\n+ uint32_t guest_bits;\n+ DeviceState *aplic_s_dev = NULL;\n+ DeviceState *aplic_m_dev = NULL;\n+\n+ if (msimode) {\n+ if (!kvm_enabled()) {\n+ /* Per-socket M-level IMSICs */\n+ addr = imsic_m->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIFT);\n+ for (i = 0; i < hart_count; i++) {\n+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),\n+ base_hartid + i, true, 1,\n+ num_msis);\n+ }\n+ }\n+\n+ /* Per-socket S-level IMSICs */\n+ guest_bits = imsic_num_bits(aia_guests + 1);\n+ addr = imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIFT);\n+ for (i = 0; i < hart_count; i++) {\n+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),\n+ base_hartid + i, false, 1 + aia_guests,\n+ num_msis);\n+ }\n+ }\n+\n+ if (!kvm_enabled()) {\n+ /* Per-socket M-level APLIC */\n+ aplic_m_dev = riscv_aplic_create(aplic_m->base +\n+ socket * aplic_m->size,\n+ aplic_m->size,\n+ (msimode) ? 0 : base_hartid,\n+ (msimode) ? 0 : hart_count,\n+ VIRT_IRQCHIP_NUM_SOURCES,\n+ num_prio_bits,\n+ msimode, true, NULL);\n+ }\n+\n+ /* Per-socket S-level APLIC */\n+ aplic_s_dev = riscv_aplic_create(aplic_s->base +\n+ socket * aplic_s->size,\n+ aplic_s->size,\n+ (msimode) ? 0 : base_hartid,\n+ (msimode) ? 0 : hart_count,\n+ VIRT_IRQCHIP_NUM_SOURCES,\n+ num_prio_bits,\n+ msimode, false, aplic_m_dev);\n+\n+ if (kvm_enabled() && msimode) {\n+ riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s_dev), addr);\n+ }\n+\n+ return kvm_enabled() ? aplic_s_dev : aplic_m_dev;\n+}\ndiff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c\nindex fd6ca5dbc4ff..145f8d92ad69 100644\n--- a/hw/riscv/virt-acpi-build.c\n+++ b/hw/riscv/virt-acpi-build.c\n@@ -42,6 +42,8 @@\n #include \"system/kvm.h\"\n #include \"system/reset.h\"\n \n+#include \"aia.h\"\n+\n #define ACPI_BUILD_TABLE_SIZE 0x20000\n #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))\n \ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex 4501d5581b62..ce0fd6f50c4a 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -59,6 +59,8 @@\n #include \"hw/virtio/virtio-iommu.h\"\n #include \"hw/uefi/var-service-api.h\"\n \n+#include \"aia.h\"\n+\n /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */\n static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)\n {\n@@ -509,17 +511,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s,\n }\n }\n \n-uint32_t imsic_num_bits(uint32_t count)\n-{\n- uint32_t ret = 0;\n-\n- while (BIT(ret) < count) {\n- ret++;\n- }\n-\n- return ret;\n-}\n-\n static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,\n uint32_t *intc_phandles, uint32_t msi_phandle,\n bool m_mode, uint32_t imsic_guest_bits)\n@@ -1293,68 +1284,6 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,\n memmap[VIRT_PLIC].size);\n }\n \n-static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,\n- const MemMapEntry *memmap, int socket,\n- int base_hartid, int hart_count)\n-{\n- int i;\n- hwaddr addr = 0;\n- uint32_t guest_bits;\n- DeviceState *aplic_s = NULL;\n- DeviceState *aplic_m = NULL;\n- bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;\n-\n- if (msimode) {\n- if (!kvm_enabled()) {\n- /* Per-socket M-level IMSICs */\n- addr = memmap[VIRT_IMSIC_M].base +\n- socket * VIRT_IMSIC_GROUP_MAX_SIZE;\n- for (i = 0; i < hart_count; i++) {\n- riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),\n- base_hartid + i, true, 1,\n- VIRT_IRQCHIP_NUM_MSIS);\n- }\n- }\n-\n- /* Per-socket S-level IMSICs */\n- guest_bits = imsic_num_bits(aia_guests + 1);\n- addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;\n- for (i = 0; i < hart_count; i++) {\n- riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),\n- base_hartid + i, false, 1 + aia_guests,\n- VIRT_IRQCHIP_NUM_MSIS);\n- }\n- }\n-\n- if (!kvm_enabled()) {\n- /* Per-socket M-level APLIC */\n- aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +\n- socket * memmap[VIRT_APLIC_M].size,\n- memmap[VIRT_APLIC_M].size,\n- (msimode) ? 0 : base_hartid,\n- (msimode) ? 0 : hart_count,\n- VIRT_IRQCHIP_NUM_SOURCES,\n- VIRT_IRQCHIP_NUM_PRIO_BITS,\n- msimode, true, NULL);\n- }\n-\n- /* Per-socket S-level APLIC */\n- aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +\n- socket * memmap[VIRT_APLIC_S].size,\n- memmap[VIRT_APLIC_S].size,\n- (msimode) ? 0 : base_hartid,\n- (msimode) ? 0 : hart_count,\n- VIRT_IRQCHIP_NUM_SOURCES,\n- VIRT_IRQCHIP_NUM_PRIO_BITS,\n- msimode, false, aplic_m);\n-\n- if (kvm_enabled() && msimode) {\n- riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);\n- }\n-\n- return kvm_enabled() ? aplic_s : aplic_m;\n-}\n-\n static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)\n {\n DeviceState *dev;\n@@ -1617,9 +1546,15 @@ static void virt_machine_init(MachineState *machine)\n s->irqchip[i] = virt_create_plic(s->memmap, i,\n base_hartid, hart_count);\n } else {\n- s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,\n- s->memmap, i, base_hartid,\n- hart_count);\n+ s->irqchip[i] = riscv_create_aia(s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC,\n+ s->aia_guests,\n+ &s->memmap[VIRT_APLIC_M],\n+ &s->memmap[VIRT_APLIC_S],\n+ &s->memmap[VIRT_IMSIC_M],\n+ &s->memmap[VIRT_IMSIC_S],\n+ i, base_hartid, hart_count,\n+ VIRT_IRQCHIP_NUM_MSIS,\n+ VIRT_IRQCHIP_NUM_PRIO_BITS);\n }\n \n /* Try to use different IRQCHIP instance based device type */\ndiff --git a/hw/riscv/meson.build b/hw/riscv/meson.build\nindex 533472e22aef..e53c180d0d10 100644\n--- a/hw/riscv/meson.build\n+++ b/hw/riscv/meson.build\n@@ -1,5 +1,5 @@\n riscv_ss = ss.source_set()\n-riscv_ss.add(files('boot.c'))\n+riscv_ss.add(files('boot.c', 'aia.c'))\n riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))\n riscv_ss.add(files('riscv_hart.c'))\n riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))\n", "prefixes": [ "v3", "05/13" ] }