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{
    "id": 2224877,
    "url": "http://patchwork.ozlabs.org/api/patches/2224877/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com>",
    "list_archive_url": null,
    "date": "2026-04-19T09:39:34",
    "name": "PCI: qcom: Disable ASPM L0s for SA8775P",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "d64f806bc450cf0f7933061adb61891ef168e0aa",
    "submitter": {
        "id": 93189,
        "url": "http://patchwork.ozlabs.org/api/people/93189/?format=api",
        "name": "Shawn Guo",
        "email": "shengchao.guo@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 500490,
            "url": "http://patchwork.ozlabs.org/api/series/500490/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500490",
            "date": "2026-04-19T09:39:34",
            "name": "PCI: qcom: Disable ASPM L0s for SA8775P",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/500490/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2224877/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2224877/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        ],
        "From": "Shawn Guo <shengchao.guo@oss.qualcomm.com>",
        "To": "Manivannan Sadhasivam <mani@kernel.org>",
        "Cc": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,\n Qiang Yu <qiang.yu@oss.qualcomm.com>, linux-pci@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,\n Shawn Guo <shengchao.guo@oss.qualcomm.com>",
        "Subject": "[PATCH] PCI: qcom: Disable ASPM L0s for SA8775P",
        "Date": "Sun, 19 Apr 2026 17:39:34 +0800",
        "Message-ID": "<20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com>",
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    },
    "content": "Commit f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port\nif iMSI-RX is used as MSI controller\") removed MSI/MSI-X capabilities\nfrom the Root Port on platforms using iMSI-RX (including SA8775P, which\nhas no msi-parent/msi-map in DT).  This causes PME and AER service\ndrivers to fall back from MSI to INTx.\n\nWith INTx-based PME active, the QCN9100 modem endpoint sends PME messages\nduring D-state transitions early in boot.  The level-triggered INTx\nassertion coincides with ASPM L0s exit sequencing on SA8775P hardware,\ncausing Data Link Layer Replay Timer Timeout errors on both sides of the\nlink.\n\n[   13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332\n[   13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332\n[   13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0\n[   13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n[   13.111281] pci 0000:01:00.0:   device [17cb:1103] error status/mask=00001000/0000e000\n[   13.111284] pci 0000:01:00.0:    [12] Timeout\n[   13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0\n[   13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n[   13.130514] pcieport 0000:00:00.0:   device [17cb:0115] error status/mask=00001000/0000e000\n[   13.130516] pcieport 0000:00:00.0:    [12] Timeout\n\nFix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true\nto cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from\nthe Root Port and ASPM L0s is prevented from being negotiated.\n\nFixes: f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller\")\nAssisted-by: Claude:claude-4-6-sonnet\nSigned-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-qcom.c | 1 +\n 1 file changed, 1 insertion(+)",
    "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex af6bf5cce65b..6a14b5091338 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -1473,6 +1473,7 @@ static const struct qcom_pcie_cfg cfg_1_9_0 = {\n static const struct qcom_pcie_cfg cfg_1_34_0 = {\n \t.ops = &ops_1_9_0,\n \t.override_no_snoop = true,\n+\t.no_l0s = true,\n };\n \n static const struct qcom_pcie_cfg cfg_2_1_0 = {\n",
    "prefixes": []
}