[{"id":3679241,"web_url":"http://patchwork.ozlabs.org/comment/3679241/","msgid":"<453jc2ff65zdn3yahdwkdh2uqzz2coi4kv3siqfygfgmfd3v4w@4dkwj3s4dkfp>","list_archive_url":null,"date":"2026-04-20T06:38:25","subject":"Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Sun, Apr 19, 2026 at 05:39:34PM +0800, Shawn Guo wrote:\n> Commit f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port\n> if iMSI-RX is used as MSI controller\") removed MSI/MSI-X capabilities\n> from the Root Port on platforms using iMSI-RX (including SA8775P, which\n> has no msi-parent/msi-map in DT). This causes PME and AER service\n> drivers to fall back from MSI to INTx.\n> \n> With INTx-based PME active, the QCN9100 modem endpoint sends PME messages\n> during D-state transitions early in boot. The level-triggered INTx\n> assertion coincides with ASPM L0s exit sequencing on SA8775P hardware,\n> causing Data Link Layer Replay Timer Timeout errors on both sides of the\n> link.\n> \n\nHow did you conclude that INTx collides with ASPM L0s exit sequence? Also,\nAFAIK, L0s is supported and work well on this chipset.\n\nWhat we are dealing with could be the board specific issue.\n\n> [ 13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332\n> [ 13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332\n> [ 13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0\n> [ 13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n> [ 13.111281] pci 0000:01:00.0: device [17cb:1103] error status/mask=00001000/0000e000\n> [ 13.111284] pci 0000:01:00.0: [12] Timeout\n> [ 13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0\n> [ 13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n> [ 13.130514] pcieport 0000:00:00.0: device [17cb:0115] error status/mask=00001000/0000e000\n> [ 13.130516] pcieport 0000:00:00.0: [12] Timeout\n> \n> Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true\n> to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from\n> the Root Port and ASPM L0s is prevented from being negotiated.\n> \n\nNo. This is not the correct fix. If we identify if this is a board issue, we\nneed to disable L0s selectively using 'pcie,no-aspm-l0s' DT property defined in\nthe Root Port DT node.\n\n> Fixes: f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller\")\n> Assisted-by: Claude:claude-4-6-sonnet\n\nOk, this seems to be an AI slop. INTx is triggered through in-band messages and\nthe link should be in L0 so that an endpoint can transmit these. So there is no\nway it could collide with L0s exit sequence as the link being in L0 is the\npre-requisite for triggering INTx.\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=amPs/eFe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52746-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"amPs/eFe\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzbfB0Jrfz1yCv\n\tfor ; Mon, 20 Apr 2026 16:48:02 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id F26403069557\n\tfor ; Mon, 20 Apr 2026 06:40:48 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id D0FA7382F02;\n\tMon, 20 Apr 2026 06:38:36 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id ADFEC382391;\n\tMon, 20 Apr 2026 06:38:36 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 85A4AC19425;\n\tMon, 20 Apr 2026 06:38:33 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776667116; cv=none;\n b=mWD2M9Ru02Xlc9J1FzMLKLMM6swlMojkB5PIGnoasEpHjg3r3m0tHroQrFLyTffe9hihXAxyF82HyFm1bJLDsQdhDp9EfwjuAMGEgNFHmXh75krGu7xEKzJeKbABIuKQl/qSgvNQrX/oIFMrrUX2ps8SGDQmu5J6I/qWi1GP1ms=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776667116; c=relaxed/simple;\n\tbh=ZY57myzLTROZkKPMgE6E+Hum6BiWgqSE7TyD0ENLE98=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=XS/dwfI03bxFpW2AZmmWYfMIZealEPHzehvuf6yoXNxEtoNT+9pzz+C10z/ixCxlplo+4KOvgCrQr6hIFM/Sy8wr+8tOIGH+J8o5MgizsyM7jtxFi10PhbTYCgYrEElxaLiVFIb23pGPmd1y07OamxBF1Pi+48BVFgJA35Wyhy0=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=amPs/eFe; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776667116;\n\tbh=ZY57myzLTROZkKPMgE6E+Hum6BiWgqSE7TyD0ENLE98=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=amPs/eFep+HnkJoSItsSZA2nIRxHS1TaOlgRxIUVxBBM+CkKVM/n+Y2x9j+vkPMVm\n\t aXczYvMC/Su2a9Q7cBLdT7yQbOpF2GF1ghkVI4emWHWcu+WVso1KwNpoiy38JFoz8C\n\t Ce55zctulKd0cHVQlDK+AU0IKsvLP744iZ4H86P+byuzV0Xle0AaSQepnBL41px+FR\n\t gAEU80m1+hNlJosrLbRJK6aVA6oX9I2kB6fW+1d7b1YqXM4S7eL/UO5RoUHLPrMiU4\n\t 04Seeq4q96gbkHAIA6W2ubyGHdYH5pPY+mgUCdxJDE0CuVSMGCM3t6OGdt1k7qo8Ie\n\t lCXluU+I9mrpg==","Date":"Mon, 20 Apr 2026 12:08:25 +0530","From":"Manivannan Sadhasivam ","To":"Shawn Guo ","Cc":"Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Rob Herring , Bjorn Helgaas ,\n Qiang Yu , linux-pci@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P","Message-ID":"<453jc2ff65zdn3yahdwkdh2uqzz2coi4kv3siqfygfgmfd3v4w@4dkwj3s4dkfp>","References":"<20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com>"}},{"id":3679654,"web_url":"http://patchwork.ozlabs.org/comment/3679654/","msgid":"","list_archive_url":null,"date":"2026-04-21T02:55:56","subject":"Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P","submitter":{"id":93189,"url":"http://patchwork.ozlabs.org/api/people/93189/","name":"Shawn Guo","email":"shengchao.guo@oss.qualcomm.com"},"content":"On Mon, Apr 20, 2026 at 12:08:25PM +0530, Manivannan Sadhasivam wrote:\n> On Sun, Apr 19, 2026 at 05:39:34PM +0800, Shawn Guo wrote:\n> > Commit f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port\n> > if iMSI-RX is used as MSI controller\") removed MSI/MSI-X capabilities\n> > from the Root Port on platforms using iMSI-RX (including SA8775P, which\n> > has no msi-parent/msi-map in DT). This causes PME and AER service\n> > drivers to fall back from MSI to INTx.\n> > \n> > With INTx-based PME active, the QCN9100 modem endpoint sends PME messages\n> > during D-state transitions early in boot. The level-triggered INTx\n> > assertion coincides with ASPM L0s exit sequencing on SA8775P hardware,\n> > causing Data Link Layer Replay Timer Timeout errors on both sides of the\n> > link.\n> > \n> \n> How did you conclude that INTx collides with ASPM L0s exit sequence? Also,\n> AFAIK, L0s is supported and work well on this chipset.\n> \n> What we are dealing with could be the board specific issue.\n\nI just got looped into an internal discussion. The issue seems to\nbe refgen voting related, so likely affects all Lemans (and Monaco)\nboards with PCIe enabled.\n\nBefore a proper fix is available, 'pcie_aspm=off' on kernel cmdline is\nsuggested as a temporary workaround.\n\n> > [ 13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332\n> > [ 13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332\n> > [ 13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0\n> > [ 13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n> > [ 13.111281] pci 0000:01:00.0: device [17cb:1103] error status/mask=00001000/0000e000\n> > [ 13.111284] pci 0000:01:00.0: [12] Timeout\n> > [ 13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0\n> > [ 13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)\n> > [ 13.130514] pcieport 0000:00:00.0: device [17cb:0115] error status/mask=00001000/0000e000\n> > [ 13.130516] pcieport 0000:00:00.0: [12] Timeout\n> > \n> > Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true\n> > to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from\n> > the Root Port and ASPM L0s is prevented from being negotiated.\n> > \n> \n> No. This is not the correct fix. If we identify if this is a board issue, we\n> need to disable L0s selectively using 'pcie,no-aspm-l0s' DT property defined in\n> the Root Port DT node.\n> \n> > Fixes: f5cd8a929c82 (\"PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller\")\n> > Assisted-by: Claude:claude-4-6-sonnet\n> \n> Ok, this seems to be an AI slop. INTx is triggered through in-band messages and\n> the link should be in L0 so that an endpoint can transmit these. So there is no\n> way it could collide with L0s exit sequence as the link being in L0 is the\n> pre-requisite for triggering INTx.\n\nThank you for the insight! Indeed, I was asking help from AI as I do not\nhave too much expertise on PCIe ;)\n\nShawn","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=X44ieAHO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=VTCAHQwr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52808-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"X44ieAHO\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"VTCAHQwr\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g06S870H5z1yGt\n\tfor ; Tue, 21 Apr 2026 12:56:08 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 730283003ED9\n\tfor ; Tue, 21 Apr 2026 02:56:06 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 76B08265CA2;\n\tTue, 21 Apr 2026 02:56:05 +0000 (UTC)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 38F981DD0EF\n\tfor ; Tue, 21 Apr 2026 02:56:03 +0000 (UTC)","from pps.filterd (m0279863.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63KHMhf01598349\n\tfor ; Tue, 21 Apr 2026 02:56:03 GMT","from mail-dl1-f69.google.com (mail-dl1-f69.google.com\n [74.125.82.69])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dnfgnm4d3-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor ; Tue, 21 Apr 2026 02:56:03 +0000 (GMT)","by mail-dl1-f69.google.com with SMTP id\n a92af1059eb24-12c66fdd4aeso5430556c88.0\n for ; Mon, 20 Apr 2026 19:56:03 -0700 (PDT)","from QCOM-aGQu4IUr3Y (i-global052.qualcomm.com. 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