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GET /api/patches/2224148/?format=api
{ "id": 2224148, "url": "http://patchwork.ozlabs.org/api/patches/2224148/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:30", "name": "[v3,01/11] PCI: Propagate FLR return values to callers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "768358ea2d80cde0e3ba5b6098bc885eed4ff352", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224148/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224148/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52661-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Q7kKQGWv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 01/11] PCI: Propagate FLR return values to callers", "Date": "Thu, 16 Apr 2026 16:28:30 -0700", "Message-ID": "\n <8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1776381841.git.nicolinc@nvidia.com>", "References": "<cover.1776381841.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ1PEPF00002314:EE_|SJ2PR12MB9085:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cec47fd0-727d-4530-dd9a-08de9c0ff696", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tNwzuOyQYKmlZK6sDqo4pjxdYG0VPidOm77eQKk3Siv0pyuSSds5R9jMNAYRl2RnQGzEZYNUlU+xYxlStttR6SH4vSsTJsaZtLERecEYh5iMtD1P4P1+rxm3eLbunNNoR0JF9EGrN6ag4ypswtmUnclgey810GVbV2mF9+Ntniy+NxtEqGiHosfhV02uIaSQpIkYLYQn3YiFnT1WHU2xNe5qDj0b0UBLirzj1at/TqiDteuXXekP9drFOgtVmLz8qNRN1ZbexQvzeDnbWYxJh5BtRR4IJjT6NIkKka4FSveFTlofH++NLWDXcuDfUcg1mo07tZ59KSUrasLvIhSgv3if5mdaspx0Gy3qBYMQMyW9SJVeubvuI3xM2P+F9BwGfkWfKYLPWdEcqfZZMmTPqYKoNNfs22hVuvJT47YFwDmd7nzK/e3cz8gBZm464flAWxobubVclHoSUQ7NNbin6fr5TeShgYZybE4HL1PKBLrYxgTHw807WBXT+jWdMiMBcu93UPxD93PUPBk1X3Kf62Q91lzY01UPyrgr2QbscxYKQpXzmEe514bUdfPvaLfkfhEgLpVr4dcDSFX1Bd8Lt+khKhP0DLd+PmAi6CXgA1K+eNq1c3u+zm12t8cLnIbKU+kNmF0vUkwBGRFnr7nJYBZgN5C3YsMQ0iaHNWHut84pfS9yq4esKAjrMzoHwVSgkfZm+R1hjsXIC91QHHyfv7YIaIDwW0BIpHqLuAtSY7QtcVQ28JblgcyLXhP1ZiRONHORT0hQr7Y3QHGn25aLFPA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tofydaOflGwO+wgh2cuIdIRQIbBwYK5RgTHdGZme6pFX04Rats5l41xFxOwBAF+ncEusCLjtK5oG1YCfsZFsAusvr21k5wtksDkGQnhafdjnoj6rOx4k0DPPmPEiUV/wOuWs43rrjIecVOoU6Nao8H3YMC7yvq5rBn8q2XVRFvhjQS/62ZbUDi7I+CZCrVE8zj+vwCxvQGwakblVqigk+/LJzVtcKzmCrnX4unsw617Y25PyTlqfRlp6TobkpBOlz0gYfz6sEKEdd+g5uDPJMarEqDwoEBu+QkdTUeIyVTLPln7yIOare2jw8a1IwfJ0LYbU+ukF7kd9dY/qxKJfVE+TtPhfzLexJlszm5jFEJcrpJ5+zdN+mtDRMTyQiKjDRkn65RddgW0hH8lijtgsbFzlR52piqG422Wws8Wa2Ij58isUeEKVCyT45RD90cmR2", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:10.7446\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cec47fd0-727d-4530-dd9a-08de9c0ff696", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF00002314.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB9085" }, "content": "A reset failure implies that the device might be unreliable. E.g. its ATC\nmight still retain stale entries. Thus, the IOMMU layer cannot trust this\ndevice to resume its ATS function that can lead to memory corruption. So,\nthe pci_dev_reset_iommu_done() won't recover the device's IOMMU pathway if\nthe device reset fails.\n\nThose functions in the pci_dev_reset_methods array invoke pcie_flr(), but\ndo not check the return value. Propagate them correctly.\n\nGiven that these functions have been running okay, and the return values\nwill be only needed for an incoming work. This is not treated as bug fix.\n\nSuggested-by: Kevin Tian <kevin.tian@intel.com>\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/pci/quirks.c | 22 ++++++++++++----------\n 1 file changed, 12 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 48946cca4be72..05ce12b6b2f76 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -3957,7 +3957,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)\n \t * supported.\n \t */\n \tif (!probe)\n-\t\tpcie_flr(dev);\n+\t\treturn pcie_flr(dev);\n \treturn 0;\n }\n \n@@ -4015,6 +4015,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n {\n \tu16 old_command;\n \tu16 msix_flags;\n+\tint ret;\n \n \t/*\n \t * If this isn't a Chelsio T4-based device, return -ENOTTY indicating\n@@ -4060,7 +4061,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n \t\t\t\t PCI_MSIX_FLAGS_ENABLE |\n \t\t\t\t PCI_MSIX_FLAGS_MASKALL);\n \n-\tpcie_flr(dev);\n+\tret = pcie_flr(dev);\n \n \t/*\n \t * Restore the configuration information (BAR values, etc.) including\n@@ -4069,7 +4070,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n \t */\n \tpci_restore_state(dev);\n \tpci_write_config_word(dev, PCI_COMMAND, old_command);\n-\treturn 0;\n+\treturn ret;\n }\n \n #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed\n@@ -4152,9 +4153,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)\n \n \tpci_iounmap(dev, bar);\n \n-\tpcie_flr(dev);\n-\n-\treturn 0;\n+\treturn pcie_flr(dev);\n }\n \n /*\n@@ -4166,14 +4165,16 @@ static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)\n */\n static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)\n {\n+\tint ret;\n+\n \tif (probe)\n \t\treturn pcie_reset_flr(dev, PCI_RESET_PROBE);\n \n-\tpcie_reset_flr(dev, PCI_RESET_DO_RESET);\n+\tret = pcie_reset_flr(dev, PCI_RESET_DO_RESET);\n \n \tmsleep(250);\n \n-\treturn 0;\n+\treturn ret;\n }\n \n #define PCI_DEVICE_ID_HINIC_VF 0x375E\n@@ -4189,6 +4190,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n \tunsigned long timeout;\n \tvoid __iomem *bar;\n \tu32 val;\n+\tint ret;\n \n \tif (probe)\n \t\treturn 0;\n@@ -4209,7 +4211,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n \tval = val | HINIC_VF_FLR_PROC_BIT;\n \tiowrite32be(val, bar + HINIC_VF_OP);\n \n-\tpcie_flr(pdev);\n+\tret = pcie_flr(pdev);\n \n \t/*\n \t * The device must recapture its Bus and Device Numbers after FLR\n@@ -4236,7 +4238,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n reset_complete:\n \tpci_iounmap(pdev, bar);\n \n-\treturn 0;\n+\treturn ret;\n }\n \n static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {\n", "prefixes": [ "v3", "01/11" ] }