[{"id":3680233,"web_url":"http://patchwork.ozlabs.org/comment/3680233/","msgid":"<cbcbea4e-c857-4b75-a55d-ba3f89cdf22d@linux.intel.com>","list_archive_url":null,"date":"2026-04-22T06:13:49","subject":"Re: [PATCH v3 01/11] PCI: Propagate FLR return values to callers","submitter":{"id":73538,"url":"http://patchwork.ozlabs.org/api/people/73538/","name":"Baolu Lu","email":"baolu.lu@linux.intel.com"},"content":"On 4/17/26 07:28, Nicolin Chen wrote:\n> A reset failure implies that the device might be unreliable. E.g. its ATC\n> might still retain stale entries. Thus, the IOMMU layer cannot trust this\n> device to resume its ATS function that can lead to memory corruption. So,\n> the pci_dev_reset_iommu_done() won't recover the device's IOMMU pathway if\n> the device reset fails.\n> \n> Those functions in the pci_dev_reset_methods array invoke pcie_flr(), but\n> do not check the return value. Propagate them correctly.\n> \n> Given that these functions have been running okay, and the return values\n> will be only needed for an incoming work. This is not treated as bug fix.\n> \n> Suggested-by: Kevin Tian <kevin.tian@intel.com>\n> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>\n> ---\n>   drivers/pci/quirks.c | 22 ++++++++++++----------\n>   1 file changed, 12 insertions(+), 10 deletions(-)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index 48946cca4be72..05ce12b6b2f76 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -3957,7 +3957,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)\n>   \t * supported.\n>   \t */\n>   \tif (!probe)\n> -\t\tpcie_flr(dev);\n> +\t\treturn pcie_flr(dev);\n>   \treturn 0;\n>   }\n>   \n> @@ -4015,6 +4015,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n>   {\n>   \tu16 old_command;\n>   \tu16 msix_flags;\n> +\tint ret;\n>   \n>   \t/*\n>   \t * If this isn't a Chelsio T4-based device, return -ENOTTY indicating\n> @@ -4060,7 +4061,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n>   \t\t\t\t      PCI_MSIX_FLAGS_ENABLE |\n>   \t\t\t\t      PCI_MSIX_FLAGS_MASKALL);\n>   \n> -\tpcie_flr(dev);\n> +\tret = pcie_flr(dev);\n\nIt makes more sense to return early here on failure. There is no need to\nperform the subsequent steps if pcie_flr() fails. Would something like\nthe following work?\n\ndiff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 757a296eae41..9e0f29ac9f95 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -4015,6 +4015,7 @@ static int reset_chelsio_generic_dev(struct \npci_dev *dev, bool probe)\n  {\n         u16 old_command;\n         u16 msix_flags;\n+       int ret;\n\n         /*\n          * If this isn't a Chelsio T4-based device, return -ENOTTY \nindicating\n@@ -4060,7 +4061,9 @@ static int reset_chelsio_generic_dev(struct \npci_dev *dev, bool probe)\n                                       PCI_MSIX_FLAGS_ENABLE |\n                                       PCI_MSIX_FLAGS_MASKALL);\n\n-       pcie_flr(dev);\n+       ret = pcie_flr(dev);\n+       if (ret)\n+               return ret;\n\n         /*\n          * Restore the configuration information (BAR values, etc.) \nincluding\n\n>   \n>   \t/*\n>   \t * Restore the configuration information (BAR values, etc.) including\n> @@ -4069,7 +4070,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n>   \t */\n>   \tpci_restore_state(dev);\n>   \tpci_write_config_word(dev, PCI_COMMAND, old_command);\n> -\treturn 0;\n> +\treturn ret;\n>   }\n>   \n>   #define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed\n> @@ -4152,9 +4153,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)\n>   \n>   \tpci_iounmap(dev, bar);\n>   \n> -\tpcie_flr(dev);\n> -\n> -\treturn 0;\n> +\treturn pcie_flr(dev);\n>   }\n>   \n>   /*\n> @@ -4166,14 +4165,16 @@ static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)\n>    */\n>   static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)\n>   {\n> +\tint ret;\n> +\n>   \tif (probe)\n>   \t\treturn pcie_reset_flr(dev, PCI_RESET_PROBE);\n>   \n> -\tpcie_reset_flr(dev, PCI_RESET_DO_RESET);\n> +\tret = pcie_reset_flr(dev, PCI_RESET_DO_RESET);\n>   \n>   \tmsleep(250);\n\nThe same there, ...\n\n>   \n> -\treturn 0;\n> +\treturn ret;\n>   }\n>   \n>   #define PCI_DEVICE_ID_HINIC_VF      0x375E\n> @@ -4189,6 +4190,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n>   \tunsigned long timeout;\n>   \tvoid __iomem *bar;\n>   \tu32 val;\n> +\tint ret;\n>   \n>   \tif (probe)\n>   \t\treturn 0;\n> @@ -4209,7 +4211,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n>   \tval = val | HINIC_VF_FLR_PROC_BIT;\n>   \tiowrite32be(val, bar + HINIC_VF_OP);\n>   \n> -\tpcie_flr(pdev);\n> +\tret = pcie_flr(pdev);\n\n\n... and here.\n\n>   \n>   \t/*\n>   \t * The device must recapture its Bus and Device Numbers after FLR\n> @@ -4236,7 +4238,7 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)\n>   reset_complete:\n>   \tpci_iounmap(pdev, bar);\n>   \n> -\treturn 0;\n> +\treturn ret;\n>   }\n>   \n>   static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {\n\nThanks,\nbaolu","headers":{"Return-Path":"\n <linux-pci+bounces-52917-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=D511bxnO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52917-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"D511bxnO\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.17","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0pv54J6Zz1yHB\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 16:18:25 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id A2000302AC3B\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 06:15:58 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 610DA23D281;\n\tWed, 22 Apr 2026 06:15:58 +0000 (UTC)","from mgamail.intel.com (mgamail.intel.com [198.175.65.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B4CB41C6A;\n\tWed, 22 Apr 2026 06:15:55 +0000 (UTC)","from fmviesa010.fm.intel.com ([10.60.135.150])\n  by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2026 23:15:55 -0700","from allen-sbox.sh.intel.com (HELO [10.239.159.30])\n ([10.239.159.30])\n  by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2026 23:15:52 -0700"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776838558; cv=none;\n b=YtcqXoGZ2/YlsTLM//fywdyOorbgKSxlb4sT1b4fY7DmG55DHH8zFD8OJE9JDyt6oWDWihap+bxcpcfG9KB9/jCTDK6ylH2G0BrB1PdsKQGvytTghHyi0yIqmHp8dGgpNR8XCUWms2320wFLl4g/kV8eFF2TSn8c17+wqNgQNoE=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776838558; c=relaxed/simple;\n\tbh=wNW80J9+6cZEODBKEuNJBOLTJ4Is+qz3rHCTGu+9o+w=;\n\th=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:\n\t In-Reply-To:Content-Type;\n b=qOZtTdXlcmIhllaVQ8NPcVG8QpPY/8qXyYYMU9TVojIItTj2eF/Es9PGJt4UCDjeaURa1LcfYgxWd1i4bge2HkE2Zc34qh/gAV7LexKvZ/QqOdEyux6OIg66s/IwN++s0VBzcIAdRK7C3+1XRjkvi/CWP/gdJXjYatu31upS02I=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com;\n spf=pass smtp.mailfrom=linux.intel.com;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=D511bxnO; arc=none smtp.client-ip=198.175.65.17","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n  d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n  t=1776838556; x=1808374556;\n  h=message-id:date:mime-version:subject:to:cc:references:\n   from:in-reply-to:content-transfer-encoding;\n  bh=wNW80J9+6cZEODBKEuNJBOLTJ4Is+qz3rHCTGu+9o+w=;\n  b=D511bxnO+G3dKFEjkzI88SGLVlzh7wSN4qGMgd/OtwVnasKefAx+JcJh\n   AH0bzEbcBL5AzLMeLNuY9ZO5VY7spSKVPYYzX/iX9pYD0kr4SuzPFCWO2\n   VAubcGnISSh8cs2KijSYr+GJiSbsL4LEu7I3XQA0B35SnhLQ30oeiwCkW\n   oXTv9u87d0PTDf8Djyipo2VTVbf85vW2bVTm4X+Rj0TgdnST16pq84Vf1\n   WxoHYyTAJWKljBpWFNxICCpJyaPXTE5DwzpySa81I4EwrBHAlYdP0TqLd\n   nnE+myWcPNwSJ+3Tag48GAoWLyZa7fdj0pk54sMKtQFVa+UY0Nz3KmOZm\n   w==;","X-CSE-ConnectionGUID":["Uqu6aBLzSbiHQ/PONe0S/g==","2R1ctoaSQaaYdcrEGlRJGA=="],"X-CSE-MsgGUID":["yNSAFwtMQ9KBcVn7pWBVpg==","RYB6JcRSSRyoZ6TmdWoRfg=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11763\"; a=\"77765898\"","E=Sophos;i=\"6.23,192,1770624000\";\n   d=\"scan'208\";a=\"77765898\"","E=Sophos;i=\"6.23,192,1770624000\";\n   d=\"scan'208\";a=\"227926992\""],"X-ExtLoop1":"1","Message-ID":"<cbcbea4e-c857-4b75-a55d-ba3f89cdf22d@linux.intel.com>","Date":"Wed, 22 Apr 2026 14:13:49 +0800","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"<linux-pci.vger.kernel.org>","List-Subscribe":"<mailto:linux-pci+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-pci+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v3 01/11] PCI: Propagate FLR return values to callers","To":"Nicolin Chen <nicolinc@nvidia.com>, Will Deacon <will@kernel.org>,\n Robin Murphy <robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jason Gunthorpe <jgg@nvidia.com>","Cc":"\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n Pranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n Kevin Tian <kevin.tian@intel.com>, linux-arm-kernel@lists.infradead.org,\n iommu@lists.linux.dev, linux-kernel@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, vsethi@nvidia.com,\n Shuai Xue <xueshuai@linux.alibaba.com>","References":"<cover.1776381841.git.nicolinc@nvidia.com>\n <8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com>","Content-Language":"en-US","From":"Baolu Lu <baolu.lu@linux.intel.com>","In-Reply-To":"\n <8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":3681272,"web_url":"http://patchwork.ozlabs.org/comment/3681272/","msgid":"<aemgLxV+bCIaLGfI@Asurada-Nvidia>","list_archive_url":null,"date":"2026-04-23T04:29:35","subject":"Re: [PATCH v3 01/11] PCI: Propagate FLR return values to callers","submitter":{"id":82183,"url":"http://patchwork.ozlabs.org/api/people/82183/","name":"Nicolin Chen","email":"nicolinc@nvidia.com"},"content":"On Wed, Apr 22, 2026 at 02:13:49PM +0800, Baolu Lu wrote:\n> On 4/17/26 07:28, Nicolin Chen wrote:\n> > @@ -4060,7 +4061,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)\n> >   \t\t\t\t      PCI_MSIX_FLAGS_ENABLE |\n> >   \t\t\t\t      PCI_MSIX_FLAGS_MASKALL);\n> > -\tpcie_flr(dev);\n> > +\tret = pcie_flr(dev);\n> \n> It makes more sense to return early here on failure. There is no need to\n> perform the subsequent steps if pcie_flr() fails. Would something like\n> the following work?\n[...]\n> @@ -4060,7 +4061,9 @@ static int reset_chelsio_generic_dev(struct pci_dev\n> *dev, bool probe)\n>                                       PCI_MSIX_FLAGS_ENABLE |\n>                                       PCI_MSIX_FLAGS_MASKALL);\n> \n> -       pcie_flr(dev);\n> +       ret = pcie_flr(dev);\n> +       if (ret)\n> +               return ret;\n\nYea, I was a bit worried to change the behavior, skipping the rest\npart. But that's probably the right thing to do.\n\nThanks\nNicolin","headers":{"Return-Path":"\n <linux-pci+bounces-53034-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Vn1OkmM4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-53034-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"Vn1OkmM4\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.201.57","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1NRY3XMSz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 14:30:01 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 71AF6300349B\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 04:29:57 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 81D09376BF2;\n\tThu, 23 Apr 2026 04:29:55 +0000 (UTC)","from CH4PR04CU002.outbound.protection.outlook.com\n (mail-northcentralusazon11013057.outbound.protection.outlook.com\n [40.107.201.57])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 257D9375AAB;\n\tThu, 23 Apr 2026 04:29:53 +0000 (UTC)","from PH8PR07CA0043.namprd07.prod.outlook.com (2603:10b6:510:2cf::28)\n by SA1PR12MB7198.namprd12.prod.outlook.com (2603:10b6:806:2bf::21) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.16; Thu, 23 Apr\n 2026 04:29:48 +0000","from SA2PEPF000015C8.namprd03.prod.outlook.com\n (2603:10b6:510:2cf:cafe::a4) by PH8PR07CA0043.outlook.office365.com\n (2603:10b6:510:2cf::28) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9791.48 via Frontend Transport; Thu,\n 23 Apr 2026 04:29:48 +0000","from mail.nvidia.com (216.228.117.160) by\n SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Thu, 23 Apr 2026 04:29:48 +0000","from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Apr\n 2026 21:29:38 -0700","from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail205.nvidia.com\n (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Apr\n 2026 21:29:38 -0700","from Asurada-Nvidia (10.127.8.12) by mail.nvidia.com (10.129.68.6)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend\n Transport; Wed, 22 Apr 2026 21:29:37 -0700"],"ARC-Seal":["i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776918595; cv=fail;\n b=BA7VywoNhcP/65Fzku/3bOQ0o1zMyI8Q0eQgInCPHEKjdm/Z1mrBd5jf498V1boZueces5bAo9UZ2GjoSMbiEhgZdQTFC6p2mRyS+zlyKT3UMJ+3He2f/a9CwvCa8JN1MuSUFvUuTTFRV4fEaim4aKRxvh0DnpS/YA5f08srngg=","i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=ChXRyXbmQ0hYqDY7lZk6pQIvc8pAz3Ntf/H7Ms6om4zSGRHfkqduq8InFsVMnn8uIsnnFqq3b+WcyypPnpdMzU5UGbLl6DkGoecuz3w+PMh9pYhGewbmiBLkzo3XJcXNBxH0L5ffPLQXdWBNccYIT7Mkm1dEyz+jGkZIpGve8XjGFljMrnrcQ5twghbvCy73AWVST/IM2b9DwBmZGBPNTOYXQW6aOM8Pybo4QW4+PkNOuZCVTiffVZKyTxX6CKBuFlBY+y/bPLhhkk6fQyZfW4Xr0xR6/NUjnT++B6CmO+C3uQkI36w9SOePSRvDFx7/J1OJPOjJiiGkDFebTuZgEA=="],"ARC-Message-Signature":["i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776918595; c=relaxed/simple;\n\tbh=ltsuNTt9fjLOOX4ENkM1/rc0hKF7o7CQL/xKItf4Ca0=;\n\th=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=mzhu+lpRj4yeQhzY+H2hVJYYVPHge1YQSXWCk9R4cRtt3on7Oo5NnC4gpF0sQ63xh97SrhjXONhwDq/F0bc9MW16JJwohJMgVV/iRDdNpo/mv2PoeFtxiInur3xTtqBenfVZ+1DA5yfpfcWVEGVPK2pkkVvICFlGZMlv1yGwuaY=","i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=L8azOsazaS+ID5+k4LSRaQ3uIeuSff7JsVjZcxmxhOU=;\n b=nsBezngxMk4F9VixMODjyIo47nZcod4e8uv8JCUWAnAklhNrtecPpGwblWTj3/PX9ud7NHdrqaL/T63qLs2mofSCUX3KapEFJlTrR+fgdUFold4l6Nnmi9str6ksatxFppEPPm+0d//VUR6HX17Bfu+hp0Z/zq+EamGUvU/dis9iqhxHe8+AAKnwZtoV6fcC0QaclBGyWEHjf5HsxmatNygCqiUqKNCdYso0Sgcu8dpejGffmyzHsR9AHksxQOCj933XogirxLe6G/ghOjhxxQiuwds+PR14UxQAIq/HLuprgLn67f1GjQysM81SsRR5I245cdqmhqUo1gJBV7MBHw=="],"ARC-Authentication-Results":["i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=Vn1OkmM4; arc=fail smtp.client-ip=40.107.201.57","i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=linux.intel.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=L8azOsazaS+ID5+k4LSRaQ3uIeuSff7JsVjZcxmxhOU=;\n b=Vn1OkmM4SdNySV/FxAWrWPspNXSr85XrLKFuTjLZOKJq6WZ6vhk4POSYPnh2OaAYEanBt6Tt88AcqKeK5RC2XkvYzQzBgooRRl1TSuulv1UHp2I3h7DzlCoHSV6aqUE9k/sTHFhn0YLwBxI5sl4iVaWsb7b7tZmDz5zLRj5WANmgMqSxvvxXWD6d5Da9bjJmKnB+uVK5GXSmAaa8lBYSiizkQJuw4B3RI68DhJC1ZtrlQSpY1MKhTEChzR8hqqiw52Ax6TvORuP9Q5BoKTmmLuBGIr+7fKmaiOBO/fGNtjF1+dJMypt83LEpaSTVpjcFHdd6PkKy91w6ZKfV2SzxiQ==","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C","Date":"Wed, 22 Apr 2026 21:29:35 -0700","From":"Nicolin Chen <nicolinc@nvidia.com>","To":"Baolu Lu <baolu.lu@linux.intel.com>","CC":"Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>, \"Rafael J . Wysocki\" <rafael@kernel.org>, \"Len\n Brown\" <lenb@kernel.org>, Pranjal Shrivastava <praan@google.com>, \"Mostafa\n Saleh\" <smostafa@google.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>","Subject":"Re: [PATCH v3 01/11] PCI: Propagate FLR return values to callers","Message-ID":"<aemgLxV+bCIaLGfI@Asurada-Nvidia>","References":"<cover.1776381841.git.nicolinc@nvidia.com>\n <8bc784e505dc04ca81582307c4a70babbf58eca0.1776381841.git.nicolinc@nvidia.com>\n <cbcbea4e-c857-4b75-a55d-ba3f89cdf22d@linux.intel.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"<linux-pci.vger.kernel.org>","List-Subscribe":"<mailto:linux-pci+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-pci+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Disposition":"inline","In-Reply-To":"<cbcbea4e-c857-4b75-a55d-ba3f89cdf22d@linux.intel.com>","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SA2PEPF000015C8:EE_|SA1PR12MB7198:EE_","X-MS-Office365-Filtering-Correlation-Id":"bc7fb18a-3f6e-4a06-4b5d-08dea0f0f424","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|1800799024|7416014|376014|36860700016|82310400026|18002099003|56012099003|22082099003;","X-Microsoft-Antispam-Message-Info":"\n\tJD1AbeDfTButLGUJlpUBnbTm4q0kSkGFB5iXVLP+TzAa5Wl3IXl4yPVcxARwx0i3Zf5oJtuAErdddpibEXtPcVut7uUkNqoN0bRAsq8GFeByW2ahHOJtwB+0sxzIVd+ruBomox9w+hsyVj3k3fwXLyllijwK5oE7+xZcZ+C6FEnVxK1QgZIbGsZwy1xARxB2vxbForMMO1B6mk9GoUGPIzZe8GeuIucteOHDiErUSm2TmgDocC9cwn+O/gy8C1k9PUYRERMXPFSZLqhKDwmKvfIxyNLzyhO9q3QPRNBV+0yfiMt6aZcTN1Mp5d/elfZ0F5gxAClKN3ft8/828ktXg5dkqwY7rc5sfc2LvghHPgcUg1SGsaxTt3VsyEizXnQASnaBbJ9/YfTujqlFWudMD41jBoVn3hNmi7QEqU8g0MXXiTf7PmDpSTi3m8LYRg/5qsdnyacjPvR9Svzr8tozrGrM64t2j/IfIYnzzWcADYWwaGfUWnBJ5zzmsouxOo1XmnROn0WalyCOtx36b4HM3M0IMRn4mb9RVVn7adLeStSG+8HaZowPg5iOFmwElP6kQj8K9uSDmPHhDhUwpPXFimDQnkuHiluq14hUv+51hLQY5tDb9LDkVDlkDkb0s/PS+ibdGLD52WVmHGbe2U0FN2XUHnMGO9s4XZsHtcIuJyguOtPvCYRDzhGp51EMvLISEgl8KHDQwNkvNbPFPd7Q4j/B2mcQzIPzLxcitZB2Vb8rqLvLJs06YH+T91JYzNcEWDbS7CB7kcc0yXYjWySulg==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700016)(82310400026)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tcGF+pptuGjS5mhaWo3/YSD54cDWIWND0UQsfvzF5w7jmKHZC7dOO3EnkTDr9G3FHvc97WmOVKmQR2pisi2Ju/y3ORFY383V62X7u5DaUAiDM1CgtIJtBdPuIHg7OvTZatLL6IxoKgavdetZMBdAmXm0I7/zWfCDlnT/YjCLQavKbZ68OCsSlqsK6RPj6AG6uasEtYWGMf1wcTPd+oArxnQc3k56/5kpD22n1gKksPxhfEyzDipjBs1WrW4EGNoi98Ut9QuXqovSE/RyA07HUVC1g7MvmkKSzw3NuUdN4HYvHcJEIylH6y3SUpPOqYs4Ltjy62UUO6GEM1N5c2AsVySDX48akZtLy2ObHW1YikqUe9OjhnYr/yr+P1aV1Du5pe0V8zNkg4tfi3wLqF/gfjN5IyKVZ5pRznhl2pafEKAjXwgq79BLWdh+Rce3cX9+F","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"23 Apr 2026 04:29:48.0580\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n bc7fb18a-3f6e-4a06-4b5d-08dea0f0f424","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tSA2PEPF000015C8.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB7198"}}]